説明

LogiCORE IP Initiator/Target v4.17 for PCI コアを Artix-7 デバイス上にインプリメントすると、次のようなタイミング エラーが発生します。

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Timing constraint: TIMEGRP "CTL_BUS" OFFSET = IN 7 ns VALID 7 ns BEFORE COMP
"PCLK" TIMEGRP         ALL_FFS;
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 153 paths analyzed, 95 endpoints analyzed, 2 failing endpoints
 2 timing errors detected. (2 setup errors, 0 hold errors)
 Minimum allowable offset is   7.005ns.
--------------------------------------------------------------------------------
Slack:                              -0.005ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:                         IRDY_N (PAD)
  Destination:                  XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5 (FF)
  Destination Clock:        CLK rising at 0.000ns
  Requirement:               7.000ns
  Data Path Delay:         12.000ns (Levels of Logic = 4)
  Clock Path Delay:        5.020ns (Levels of Logic = 2)
  Clock Uncertainty:       0.025ns

  Clock Uncertainty:                0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):        0.000ns
    Discrete Jitter (DJ):           0.000ns
    Phase Error (PE):             0.000ns

  Maximum Data Path at Slow Process Corner: IRDY_N to XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M22.I                Tiopi                 2.129   IRDY_N
                                                       IRDY_N
                                                       XPCI_WRAP/XPCI_IRDY/IBUF
    ILOGIC_X0Y119.D      net (fanout=1)        0.000   XPCI_WRAP/IRDYI
    ILOGIC_X0Y119.O      Tidi                  5.701   XPCI_WRAP/IRDYF
                                                       XPCI_WRAP/XPCI_IRDYD
                                                       ProtoComp10.IMUX.3
    SLICE_X0Y119.D6      net (fanout=13)       0.887   XPCI_WRAP/IRDYF
    SLICE_X0Y119.D       Tilo                  0.124   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PAR_CE
                                                       XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PCI_CE_SW0
    SLICE_X0Y119.C5      net (fanout=1)        0.278   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/N14
    SLICE_X0Y119.C       Tilo                  0.124   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PAR_CE
                                                       XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PCI_CE
    OLOGIC_X0Y55.OCE     net (fanout=36)       2.280   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_CE
    OLOGIC_X0Y55.CLK     Tooceck               0.477   XPCI_WRAP/ADO<5>
                                                       XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5
    -------------------------------------------------  ---------------------------
    Total                                     12.000ns (8.555ns logic, 3.445ns route)
                                                       (71.3% logic, 28.7% route)

  Minimum Clock Path at Slow Process Corner: PCLK to XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    J19.I                Tiopi                 1.961   PCLK
                                                       PCLK
                                                       XPCI_WRAP/XPCI_CLK1
    BUFGCTRL_X0Y31.I0    net (fanout=1)        1.492   XPCI_WRAP/CLK_NUB
    BUFGCTRL_X0Y31.O     Tbccko_O              0.105   XPC

ソリューション

これは既知の問題で、コアの v4.18 で修正されています。 

この問題を回避するには、タイミング エラーが発生しているネットのファブリック遅延を 2 タップ分減らします。 

上記の例では、UCF で IRDY (ソース ピン) ファブリック遅延を 2 タップ分減らします。

改訂履歴
2012/07/25 - 初版
2014/09/18 - この問題は修正済み。詳細は (ザイリンクス アンサー 52452) を参照