The following are known issues for v9.2 of this core at time of release:
1. Importing an XCO file alters the XCO configurations
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
CR 467240 AR 31379
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write.
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. For more information and additional workaround see Answer Record 41099.
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
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Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.