We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5129

LogiCORE PCI32: What is the advantage of using the BAR_x_WR/RD signals as refered to in the User Guide?


General Description: 


What is the advantage of using the BAR_x_WR and BAR_x_RD signals  

generated from the BASE_HIT[x] signal to decode the target transactions 

as opposed to using the S_WRDN signal in combination with uniquely 

decoded address signals (which have the same timing as BAR_x_WR and 



Base_Hit[x] denotes the starting address of the any BAR[x] to which 

application is configured to(either to memory or I/O space). The 

application address range is determined by BAR[x] size 

(from 16 bytes to 2GB bytes). By using BASE_HIT[x], application need 

not decode the full address and saves some logic by just decoding  

{log(BAR[x] size)} bits.

AR# 5129
日付 05/14/2014
ステータス アーカイブ
タイプ 一般