Cadence Verilog-XL issues the following warning when I simulate the LogiCORE PCI interface:
Timing violation in bic_pci_stm.bic_pci_top.\PCI_CORE/PCI_LC/PCI-AD/IO9/IFD/$1I37/X_FF
$setup( IN:298578982, posedge CLK &&& in_clk_enable:298579228, 360:360 );"
What does this warning mean?
In order to meet timing, the LogiCORE PCI turns on its AD drivers during the clock cycle BEFORE it asserts FRAME#. Therefore, the value on AD may change any time between the start of the clock cycle before FRAME# and the end of the clock cycle DURING which FRAME# is asserted. If the change occurs within the setup/hold window around the intermediate clock edge, a violation will occur when the AD IOB's input FF tries to clock in the value.
Because the core does not rely on this indeterminate value, this warning may be safely ignored.