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AR# 5178

OBSOLETE: VERILOG-XL: Timing violation: $recovery(posedge CLKB: 800, posedge CLKA: 800, 1.0: 10) with Alliance 1.5


Keywords: RAMB, RAM-block, Verilog-XL

Urgency : Standard

General Description:
When performing a functional simulation of a Virtex BlockRAM with
Verilog-XL, the following timing violation is reported on the BlockRAM.
What does this timing violation mean?

xxx: Timing violation in top.U1
$recovery(posedge CLKB: 800, posedge CLKA: 800, 1.0: 10);


This is fixed in the Xilinx Alliance 2.1

The UNISIM Virtex BlockRAM Verilog model in Alliance 1.5i incorrectly models
the relationship between the BlockRAM clocks. It does not allow both clocks
on a BlockRAM to change at the same time. This is not accurate behavior in
the case of a read.

The $recovery statement can be made conditional to the 2 input address ports
accessing the same memory location. A simple 4 line change to the Verilog
model is all that is necessary to correctly sense the timing error.

The idea is that the clock edges can't come in at the same time when the 2
port addresses are the same. Add the following code the RAMB model:

// add near the top of the file (among other declarations)
reg addr_equal;

// at the end of the file add and modify the code to:

always @(addra_int or addrb_int) begin
if (addra_int == addrb_int)

(CLKA => DOA) = (1, 1);
(CLKB => DOB) = (1, 1);
$recovery (posedge CLKB, posedge CLKA &&& addr_equal, 1,
$recovery (posedge CLKA, posedge CLKB &&& addr_equal, 1,

The 'always' statement just sets the variable 'addr_equal' to 1 if the
addresses happen to be equal. The recovery statements are made
conditional to this event by adding the '&&&' operator.

The $recovery is a Verilog system task which limits a change in an
asynchronous control signal and the next clock pulse. Please see
(Xilinx Solution 1655) for details about the $recovery system task.
AR# 5178
日付 06/29/2000
ステータス アーカイブ
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