UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5213

1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices

説明

General Description: TRCE reports large delays for specific longlines

in the 4000XV devices.

ソリューション

In the 1.5i speed files for the XV devices there is an incorrect parameter

value. This causes the delays associated with specific longlines to have

the incorrect delay.

This is can be resolved by installing the latest speed file updates. They

are available on the Xilinx FTP Site:

For the Workstation:

http://www.xilinx.com/txpatches/pub/swhelp/M1.5i_updates/15i_sp2_4kxv_data.tar.gz

For the PC:

http://www.xilinx.com/txpatches/pub/swhelp/M1.5i_updates/15i_sp2_4kxv_data.exe

AR# 5213
作成日 12/14/1998
最終更新日 01/18/2010
ステータス アーカイブ
タイプ 一般