UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52860

14.4 EDK, AXI Infrastructure - How do I connect different bus protocols? Which bridges are available?

説明

How do I connect peripherals with different bus standard protocols?

ソリューション

Xilinx provides bus IP to enable connectivity between different bus interface protocols.

The following processor bus bridges are currently offered as part of the Embedded Development Kit (EDK):

  • AHB-Lite to AXI Bridge
  • AXI to AXI Connector and AXI Interconnect
  • AXI4 to AHB-Lite Bridge
  • AXI Chip to Chip Bridge
  • AXI to PLBv46 Bridge
  • PLBv46 to AXI Bridge

For more information on the different types of bridges and their specifications, please reference their individual data sheets. Documentation for Xilinx IP can be found on the Product Support & Documentation page.

Additionally, Vivado users can make use of the AXI Protocol Converter; it connects one AXI4, AXI3, or AXI4-Lite master to one AXI slave of a different AXI memory-mapped protocol.

AR# 52860
日付 02/14/2013
ステータス アクティブ
種類 一般
デバイス
  • Zynq-7000
  • FPGA Device Families
ツール
  • Vivado
  • ISE Design Suite
  • PlanAhead
  • More
IP
  • AXI Interconnect
  • AXI to AXI Connector
このページをブックマークに追加