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AR# 53320

Zynq - XPS 14.x - MIG を使用して PL の 7 シリーズ DDRX メモリ コントローラーを PS とインターフェイスさせる方法

説明

MIG (Memory Interface Generator) を使用して PL の 7 シリーズ DDRx コントローラーを PS とインターフェイスさせるデザインを作成したいと思います。

ソリューション

MIG を使用して PL の DDRX メモリ コントローラーを PS とインターフェイス
 
1.EDK XPS 14.3/14.4 ツールを開きます。
2.Base System Builder (BSB) プロジェクトを新規作成し、[AXI Interface]を選択します。
3. [Zynq ZC706 Evaluation Platform] を選択します。
4. [Next] および [Finish] をクリックして、BSB ウィザードを終了させます。
5. IP カタログから [Memory and Memory Controllers]
を選択します。ダブルクリックまたは右クリックして、AXI 7 シリーズ メモリ コントローラー (DDRx) をデザインに追加します。ザイリンクスの MIG ウィンドウが開きます。

MIG を使用して PL に DDR3 デザインを作成

1. CORE Generator から MIG ウィザードを起動します。
2.[AXI4 interface] を選択し、[Next] をクリックして続行します。
3. [DDR3 SDRAM] を選択し、[Next] をクリックして続行します。
4. UDIMM、MT8JTF12864HZ-1G6G1 を選択して、[Next] をクリックして続行します。
5.内部終端インピーダンスを 50 に設定します。
6.ピン/バンク選択モードの画面で、固定ピン配置 I/O が使用されるように選択します。
7. MIG ツールを使用して UCF を確認します。
8. MIG を使用して DDR3 メモリをコンフィギュレーションする場合は、以下の UCF を使用してください。
9.MIG により特定バンクが DDR3 メモリ コントローラーに割り当てられます。
10. MIG を使用して PL にシステムを作成した後、ZC706 ボード用に以下の UCF を変更します。

NET "DDR_WEB"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N23" ;
NET "DDR_VRP"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M21" ;
NET "DDR_VRN"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N21" ;
NET "DDR_RAS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N24" ;
NET "DDR_ODT"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L23" ;
NET "DDR_DRSTB"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F25" ;
NET "DDR_DQS[3]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "L28" ;
NET "DDR_DQS[2]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "G29" ;
NET "DDR_DQS[1]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C29" ;
NET "DDR_DQS[0]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C26" ;
NET "DDR_DQS_n[3]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "L29" ;
NET "DDR_DQS_n[2]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "F29" ;
NET "DDR_DQS_n[1]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B29" ;
NET "DDR_DQS_n[0]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B26" ;
NET "DDR_DQ[9]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A27" ;
NET "DDR_DQ[8]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A29" ;
NET "DDR_DQ[7]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E27" ;
NET "DDR_DQ[6]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D26" ;
NET "DDR_DQ[5]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E26" ;
NET "DDR_DQ[4]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B25" ;
NET "DDR_DQ[3]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D25" ;
NET "DDR_DQ[31]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M30" ;
NET "DDR_DQ[30]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L30" ;
NET "DDR_DQ[2]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B27" ;
NET "DDR_DQ[29]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M29" ;
NET "DDR_DQ[28]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K30" ;
NET "DDR_DQ[27]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J28" ;
NET "DDR_DQ[26]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J30" ;
NET "DDR_DQ[25]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K27" ;
NET "DDR_DQ[24]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J29" ;
NET "DDR_DQ[23]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F30" ;
NET "DDR_DQ[22]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G30" ;
NET "DDR_DQ[21]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F28" ;
NET "DDR_DQ[20]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E30" ;
NET "DDR_DQ[1]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E25" ;
NET "DDR_DQ[19]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E28" ;
NET "DDR_DQ[18]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H28" ;
NET "DDR_DQ[17]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G27" ;
NET "DDR_DQ[16]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H27" ;
NET "DDR_DQ[15]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D29" ;
NET "DDR_DQ[14]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D28" ;
NET "DDR_DQ[13]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D30" ;
NET "DDR_DQ[12]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C28" ;
NET "DDR_DQ[11]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A28" ;
NET "DDR_DQ[10]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A30" ;
NET "DDR_DQ[0]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A25" ;
NET "DDR_DM[3]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K28" ;
NET "DDR_DM[2]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H29" ;
NET "DDR_DM[1]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B30" ;
NET "DDR_DM[0]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C27" ;
NET "DDR_CS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N22" ;
NET "DDR_CKE"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M22" ;
NET "DDR_Clk"   IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "K25" ;
NET "DDR_Clk_n"   IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "J25" ;
NET "DDR_CAS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M24" ;
NET "DDR_BankAddr[2]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M25" ;
NET "DDR_BankAddr[1]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M26" ;
NET "DDR_BankAddr[0]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M27" ;
NET "DDR_Addr[9]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J23" ;
NET "DDR_Addr[8]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F27" ;
NET "DDR_Addr[7]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K22" ;
NET "DDR_Addr[6]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H26" ;
NET "DDR_Addr[5]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G24" ;
NET "DDR_Addr[4]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J26" ;
NET "DDR_Addr[3]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G25" ;
NET "DDR_Addr[2]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L27" ;
NET "DDR_Addr[1]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K26" ;
NET "DDR_Addr[14]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J24" ;
NET "DDR_Addr[13]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H23" ;
NET "DDR_Addr[12]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K23" ;
NET "DDR_Addr[11]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H24" ;
NET "DDR_Addr[10]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G26" ;
NET "DDR_Addr[0]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L25" ;
 
11. [Edit Current EDK IP configuration] タブをクリックし、[Next] をクリックします。
12. [Next] および [Finish] をクリックします。
13. インスタンシエーションと IP 接続のウィンドウが開き、[OK] をクリックします。
14. XPS のウィンドウに戻り、[Bus Interfaces] タブをクリックし、メモリ コントローラーが追加されていることを確認します。
15. [Generate Netlist] をクリックします。
16. [Generate Bit Stream] をクリックします。
AR# 53320
日付 11/13/2017
ステータス アクティブ
種類 一般
デバイス
  • Zynq-7000
ツール
  • EDK - 14.3
IP
  • Memory Interface
Boards & Kits
  • Zynq-7000 SoC ZC706 Evaluation Kit
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