AR# 5334
|FPGA Express 3.x: Instantiating LUTs for Virtex/E designs
説明
Keywords: Express, Foundation, instantiate, VHDL, Verilog, Virtex, VirtexE, LUT, EQNUrgency: Standard
General Description:
FPGA Express 3.x (or Foundation F1.5i or F2.1i) does not maintain instantiations
of LUT primitives for Virtex/E designs.
This solution record describes a way to create the desired logic in the
Foundation Schematic Editor to be instantiated as a black box in FPGA Express.
ソリューション
The workaround is to create a macro in a Foundation schematic and instantiate thismacro as a black box. Follow these steps:
1. Ensure the Virtex library is defined in your HDL project. If the Virtex library is
not listed in the Files tab of your Foundation project, select File-> Project Libraries.
Select "virtex" under "Attached Libraries" and click on the Add button, then click
on the Close button.
2. Open the schematic editor. Create a schematic that contains only the LUT
instances that you wish to use (or more components, if you wish). Be sure to add
the INIT attribute to define the logic within each LUT component. Complete the
schematic by attaching nets to all the pins you wish to use. Use I/O terminals and
labels to define the I/O of this macro.
The schematic will look something like this:
Figure 1- LUT schematic with attribute
3. Use File -> Save As to save this schematic with a unique name. DO NOT use
the same name as one of the LUT primitives (or any other library name) and do not
use the name of the project.
4. Select Options -> Create Netlist from Current Sheet to write the netlist (an .ALB file).
5. Select Options -> Export Netlist. Make sure the .ALB file listed matches the
schematic you have created. DO NOT change directories; save this .EDN file
(do not select .XNF) in the current Foundation Project. Click Open to save.
6. Close the schematic editor. Note that the schematic does not show up in the Files tab.
DO NOT add the schematic or .EDN file to this project. Because this macro is to be
instantiated as a black box, Express must have no knowledge of the contents of this macro.
7. Instantiate the macro in your HDL code. Use the names of the I/O terminals in the
schematic as the port names in your HDL instantiation.
8. Because the .EDN file exists in the project directory, the Translate phase of
Implementation will merge this macro with your top-level design. If you would like to use
this macro in other designs, simply copy the .EDN file to another project directory.
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| AR# 5334 | |
|---|---|
| 日付 | 08/27/2001 |
| ステータス | アーカイブ |
| 種類 | 一般 |
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