AR# 53547

Zynq DMA cycle - Is it possible to break up the DMA cycle?


Customer had the following questions regarding the DMA transfer  cycle?

are there any requirements on the data breakup?​​ (byte or word boundary). Can the user specify any kind of length?​​

64 byte source address alignment
64 byte dest address alignment
Length can be as small as 1 word

Length should be 64 byte unless its the last transfer.

Is it always interrupt driven or can the user do a polled mode?​​

it can be driven either polled or interrupt. This is an interrupt example. Cross reference with UG 585 pg 175

•    Total image size is 4096 bytes
•    Image is aligned to 64-byte boundary.
•    User wants to transfer image in 1024 byte pieces with interrupts after each transfer.
•    Image is an unencrypted bitstream.

Recommended operation:
1.    Set the DMA source address register with last two bits set to “01” (enable DMA done interrupt).
2.    Set the DMA destination address register to 0xFFFFFFFF.
3.    Set the DMA source length register to 1024/​4 (word transfers).
4.    Set the DMA destination length register to 1024/​4 (word transfers).
5.    When interrupt occurs write a new DMA source address incremented by 1024 bytes.
6.    Repeat steps 2-5 till image transfer is complete.


Insert Solution Here
AR# 53547
日付 03/17/2020
ステータス 共有
種類 一般