AR# 5364: 1.5i XC4000X* PAR - Express designs with non-RLOC'd carry chains and Coregen modules may not place.
1.5i XC4000X* PAR - Express designs with non-RLOC'd carry chains and Coregen modules may not place.
Express is now creating non-RLOC'd carry chains in designs. This was done to fix a bug where they partially RLOC'd carry chains.
Cases have been seen where Express designs with instantiated Coregen modules are having parts of these unconstrained carry chains merged into the Coregen macro. This is occurring because parts of the Coregen macro are unused and being trimmed by map, making room for external logic to be merged in.
PAR is unable to place the resulting partially RLOC'd carry chain. Failure mode:
ERROR:x4kpl:368 - RPM "multiplier_q_inst/hset" contains a partial carry logic chain.
The problem usually involves FMAPs that drive flops being trimmed from the design. If the FMAPs are trimmed, it leaves room in the CLB for external carry chains to be merged in.
The problem is that part, but not all of a non-RLOC'd carry chain is being merged into the macro.
Currently, the only work around found has been to prevent trimming in the Coregen modules by placing nomerge attributes on key FMAP nets.
Example of .ucf syntax to prevent trimming: NET "multiplier_q_inst/N141" KEEP ; NET "multiplier_i_inst/N141" KEEP ;
Contact Xilinx support and refer to this solution record if you are seeing this problem, and need help identifying the nets involved.