説明

The ZC706 Evaluation Kit Checklist is useful to debug board-related issues and to determine if requesting a Boards RMA is the next step.

Before working through the ZC706 Board Debug Checklist, please review (Xilinx Answer 51899) - Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record, as the issue you are faced with may be covered there.

ソリューション

1.   Switch / Jumper Settings
2.   Board Power
3.   Cable detection
4.   JTAG Initialization

The following debug steps assume steps 1-4 have been checked and are working:
5.   JTAG Configuration
6.   QSPI Flash Configuration
7.   SD Card
8.   XADC
9.   PCIe
10. IBERT
11. DDR3
12. Ethernet
13. Interface Tests
14. Known Issues for ZC706


1.   Switch / Jumper Settings
      
       Default Switch and Jumper Settings for the ZC706 are:
      
       Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.

a.    ZC706 Default Switch Settings:
    

 

b.   ZC706 Default Jumper Settings:
      

    

d.     Default XADC Jumper Settings:
      

2.  Board Power
 
     Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the ZC706 Evaluation Kit. The status of Power-ON LEDs is an indication of board health.

a. Check the status of the following LEDs at Power-ON:
 

b.    If these LEDs above are not lit at power on, you may need to reprogram the TI Power Controllers on your board. This can be done using the Texas Instruments Fusion Digital Power Manufacturing tool software package, the Texas Instruments USB Interface Adapter EVM, and the appropriate XML script.
       For more details, see (Xilinx Answer 37561); and see (Xilinx Answer 56811) for information on the appropriate XML files to be used (these are board specific).
       If you do not have a TI USB Interface Adapter EVM, you can follow the steps in (Xilinx Answer 54022) to order one. This cable arrives within days and is a vital debug tool.
       Ordering the TI USB Interface Adapter EVM and reprogramming the power controllers is an important step in attempting to restore board functionality.
c.    If 12V DC Power ON LED (DS22) is not Green, then 12VDC is not being delivered to the ZC706 power input connector.  Follow these steps:
      

If the above steps fail to enable you to restore power to your board, please review the Support Webpage for your available Support options.

3.  Cable detection

     The ZC706 uses a USB A-to-micro-B cable plugged into the ZC706 Digilent USB-to-JTAG module, U30.  A Platform cable header (J3) and flying lead header (J62) are also provided for JTAG configuration.
     The JTAG chain can be programmed by any of these three methods made available via 3-to-1 analog switch (U45, U46, U47) controlled by a 2-position DIP switch at SW4.
     To ensure you have the ZC706 setup correctly  to connect to the cable of your choosing, please see JTAG Programming Option Selection below:
   

a.    USB A-to-micro-B cable
        i.   Is the cable visible in Device Manager?  If the 3 items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.

      ii.    Are cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.
             (For installation, please follow the guidelines in the document provided in the downloaded files): http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.

             This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux.  Adept software is available from Digilent: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.
      iii.   Check system properties and environment variables.  For information on environment variables, please see (Xilinx Answer 11630).
      iv.    Is the USB port enabled?  User can reboot their system to re-initialize the USB buses.
       v.    Is the latest version of Xilinx tools, supporting this kit, correctly installed?  (iMPACT or ChipScope Pro)  (For supported SW version information, please see Kit Product Page: ZC706)
             If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the ZC706)
      vi.    Is the Operating System (OS) being used Windows 7?  If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).
     vii.    Is SW4 set correctly?      

     If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

b.  Platform Cable USB II
     i.   Is the cable visible in Device Manager?
     ii.  Are the cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with the Platform Cable USB II connectionn, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).
     iii. Check system properties and environment variables.  For information on environment variables, please see (Xilinx Answer 11630).
     iv.  Is the USB port enabled?  User can reboot their system to re-initialize the USB buses.
      v.  Is the latest version of Xilinx tools, supporting this kit, correctly installed?  (iMPACT or ChipScope Pro)  (For supported SW version information, please see Kit Product Page: ZC706)
          If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the ZC706)
     vi.  Is the Operating System (OS) being used Windows 7?  If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).
    vii.  Is SW4 set correctly?

     If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

c.  Parallel Cable IV
     i.   Are the cable drivers loaded correctly?  See (Xilinx Answer 9984) for more information.
     ii.  If you receive the following message in iMPACT: 'ERROR: Device Control LPT_WRITE_CMD_BUFFER Failed' see (Xilinx Answer 22293).
     iii. Note: Parallel Cable IV speed cannot be modified in iMPACT 13.x and 12.x see (Xilinx Answer 41808) for more details.
     iv.  If you cannot establish a connection with the Parallel Cable IV, see (Xilinx Answer 15742).
      v.  Is SW4 set correctly?
 
      If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

4.  JTAG Initialization
     The status of the board JTAG chain is checked using Xilinx Tolls (iMPACT or ChipScope Pro).  To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:

a. Remove any FMC cards from ZC706
b. Set the mode switch SW4 to 01 - for Digilent USB-to-JTAG interface U30
c. Power up ZC706 on the bench (not in a PC chassis)
d. Connect the Digilent USB A-to-micro-B cable to the ZC706 through the Digilent onboard USB-to-JTAG configuration logic module - U30
e. Check Digilent device shows up in Device Manager
f.  Ensure Xilinx tools (the latest version which supports ZC706) are correctly installed
g. Launch iMPACT - is the cable identified correctly?
    i.   If not, see section 3. Cable detection above.
    ii.  If yes, but iMPACT did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup)
    iii. If yes, but iMPACT did not discover and display the JTAG chain, and slowing down the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U23):
     

    If the above steps fail to enable you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.  Connect the Platform Cable USB to header J3, and connect to your PC.
    Ensure Xilinx tools (preferably the latest version of tools that support the ZC706) are correctly installed.  Launch iMPACT - is the cable identified correctly?

    If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

5.    JTAG Configuration

       If the JTAG chain initializes OK, but JTAG configuration fails, check the following:

a.   In iMPACT, select a lower cable frequency and re-attempt configuration
b.   In iMPACT, run the Chain Integrity test by selecting Debug > Chain Integrity Test.  IMPACT will assist in the debugging of this scenario by providing insight into where the failing connection in the chain could be.
c.   Pulse the PROG push button on the ZC706 (SW10).  Pulsing PROG will clear out any problems caused by power up ramp rate issues with the PL.
d.   Read back the FPGA Status Register in IMPACT (Debug > Read Status Register).  The information extracted from the Status Register can help determine the stage of configuration and where a failure has occurred.  See (Xilinx Answer 24024) for more details.
e.   Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.
     
      If the above steps fail to enable JTAG configuration, please review the Support Webpage for your available Support options.

6.  QSPI Flash Configuration

     The Quad-SPI Flash memory located at U58 and U59 provides 2 x 128 Mb of non-volatile storage that can be used for configuration and data storage (PS).

a.  To confirm the QSPI interface on the board is working using a known working example design, download and run the ZC706 Restoring Flash Contents Design Files, whichever version is appropriate for your silicon and software version.
      It is recommended to always use the latest version of software which supports the ZC706, and the associated version of the ZC706 Restoring Flash Contents Design Files.
      Follow the associated PDF.  All are available from the ZC706 Example Designs page.
      ZC706 Restoring Flash Contents Design Files:  rdf0245.zip
      ZC706 Restoring Flash Contents PDF:                  xtp247.pdf
      To identify the silicon version of your kit, please see (Xilinx Answer 37579).
      Read the ZC706 Restoring Flash Contents design document: ZC706 Restoring Flash Contents PDF: xtp247.pdf and follow the instructions therein.
b.   If you have loaded an .mcs file into the QSPI flash on the ZC706, and subsequent boot to the XC7Z045 device fails, the following points should be checked:
      i.   In iMPACT, select a lower cable frequency and re-attempt configuration.
      ii.  Pulse the PROG push button on the ZC706 (SW10), to attempt to reload the FPGA with the configuration image.
      iii. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.

     If the above steps fail to enable BPI configuration, please review the Support Webpage for your available Support options.

7.  SD Card

As SD card which slots into SD card connector (J30) can be used for PS Configuration by means of a Processor System Boot from SD card. Information about the SD I/O card specification can be found at the SanDisk Corporation or SD Association websites.

a.   Verify SD card is inserted correctly into its socket.
b.   Verify the contents of the SD card as follows:
      i. Insert SD card into an SD reader / SD slot in PC monitor and check contents are as intended.  Are the files from which to boot located in the root directory?
      ii. The SD card will appear as "Removable Disk" on your Computer; an example directory structure, with example contents of an SD card, can be found below:

      iii. Having verified the SD card content and the directory structure, eject the SD card correctly as shown below:
    

     If the above steps fail to resolve the issue, please review the Support Webpage for your available Support options.

8.  XADC

     The XC7Z045 SoC provides an Analog Front End XADC block.  The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Converter (XADC) and on-chip sensors.

a.  Verify XADC jumper settings - see Section 1. Switch / Jumper settings, part d, above.
b.  Ensure Xilinx tools (latest version which support ZC706) are correctly installed on your machine.
c.  Details on XADC operation can be found in UG480 and UG772.  (Be sure to use the most recent version of the document)

     If the above steps fail to resolve the XADC issue, please review the Support Webpage for your available Support options.

9.  PCIe
 
     If the ZC706 configures correctly, however the PCIe interface does not operate as expected, check the following:

a.  Do NOT plug a PC ATX power supply 6-pin connector into J22 on the ZC706 board.  The ATX 6-pin connector has a different pinout than J22.  Connecting an ATX 6-pin connector into J22 will damage the ZC706 board and void the board warranty.
     To install and power the board correctly, follow the instructions given in UG954 ZC706 Evaluation Board User Guide - Appendix D - Board Setup.
b.  If you are using a Z77 (Ivy Bridge) platform, and are attempting to run the ZC706 PCIe Targeted Design, please see (Xilinx Answer 52656) - Zynq-7000 SoC ZC706 Evaluation Kit, PCIe TRD (v1.0) - PCIe does not link up successfully on Z77 (Ivy Bridge) platforms.
c.  Check J49, the lane width, is set correctly for your application.
d.  If the ZC706 you received does not have the ATX (PCIe) MiniFit Jr. adapter included in the box, please see (Xilinx Answer 53174).
e.  See (Xilinx Answer 40469) - 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for all Versions for Known Issues affecting 7-Series, including Zynq-7000.
f.   Download and run the ZC706 PCIe Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the ZC706, and associated version of the ZC706 PCIe Example Design.
     Follow the associated PDF.  All are available from the ZC706 Example Designs page.
     ZC706 PCIe Design Files: rdf0244.zip
     ZC706 PCIe PDF:                xtp246.pdf
     To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
f.   Read the ZC706 PCIe design document: ZC706 PCIe PDF: xtp246.pdf and follow the instructions therein.
g.  Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.  The Solution Center PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.

     If the above steps fail to resolve the PCIe issue, please review the Support Webpage for your available Support options.

10. IBERT

      Note: Running IBERT requires the installation of ChipScope.  A device-locked license for this software is provided with the Zynq-7000 SoC ZC706 Evaluation Kit.
      If the ZC706 configures correctly, but IBERT does not operate as expected, check the following:

a.  If using MGT loopback, ensure you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:

     More information can be found in the ZC706 GTX IBERT PDF, from the ZC706 Example Designs page.
b.  Download and run the ZC706 GTX IBERT Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the ZC706, and associated version of the ZC706 GTX IBERT Example Design.
     Follow the associated PDF.  All are available from the ZC706 Example Designs page.
     ZC706 GTX IBERT Design Files: rdf0241.zip
     ZC706 GTX IBERT PDF:                 xtp243.pdf
     To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
c.  Read the ZC706 GTX IBERT Example Design document: ZC706 GTX IBERT PDF: xtp243.pdf and follow the instructions therein.
d.  Review (Xilinx Answer 45201) - Xilinx ChipScope Solution Center - IBERT Design Assistant.  The ChipScope Solution Center is available to address all questions related to ChipScope.

     If the above steps fail to resolve the IBERT issue, please review the Support Webpage for your available Support options.

11. DDR3
 
If a problem is suspected with DDR3 / MIG, check the following:

a.  Ensure DDR3 SODIMM module is inserted correctly.
b.  Download and run the ZC706 MIG  Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software, and associated version of the ZC706 MIG Example Design.
     Follow the associated PDF.  All are available from the ZC706 Example Design page.
     ZC706 MIG Design Files: rdf0242.zip
     ZC706 MIG PDF:                 xtp244.pdf
     To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
c.  Read the ZC706 MIG Example Design document: ZC706 MIG PDF: xtp244.pdf
d.  Review (Xilinx Answer 34243) - Xilinx MIG Solution Center.  The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.

     If the above steps fail to resolve the DDR3 issue, please review the Support Webpage for your available Support options.

12. Ethernet

    The ZC706 LwIP Ethernet Design can be used to test Ethernet functionality, and is included as part of the ZC706 BIST Design Files package.  This design allows you to send packets which are then echoed back.
a. To run the LwIP Ethernet Design files, download the ZC706 BIST PDF file and follow carefully the instructions from page 42. The ZC706 BIST PDF and ZC706 BIST Design Files are available from the ZC706 Example Designs page.
     ZC706 BIST Design Files: rdf0240.zip 
     ZC706 BIST PDF:                 xtp242.pdf
     To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
b.  Review (Xilinx Answer 38279) - Ethernet IP Solution Center.  The Ethernet IP Solution Center is available to address all questions related to the Xilinx solutions for Ethernet IP.

    If the above steps fail to resolve the DDR3 issue, please review the Support Webpage for your available Support options.

13. Interface Tests

       (Xilinx Answer 54134) - Zynq-7000 SoC ZC706 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the ZC706 are working correctly.  This answer record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
       If the above tests fail to resolve the issue, please review the Support Webpage for your available Support options.

14. Known Issues for ZC706

      All Known Issues for the Zynq-7000 SoC ZC706 Evaluation Kit are listed in (Xilinx Answer 51899) - Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record.
      If the issue you are faced with is not listed in this answer record, and debug fails to resolve the issue, please review the Support Web page for your available Support options.

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