We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 5405

FPGA Express 3.x: INOUT port declaration synthesized as an output only (FE-PMAP-18)


Keywords: inout, port, output, synthesis, fpga, express, bidirectional, bus, VHDL, Verilog

Urgency: Standard

General Description:
Upon creating an implementation from within FPGA Express for an HDL file with
an INOUT declaration, FPGA Express generates a warning indicating that the
type INOUT is unknown. Then Express infers an OUT type in place of the INOUT.


Make sure that all signals declared as bidirectional are actually used as both input
and output. See (Xilinx Solution 3296) for more details.

The above warnings usually occur when there are multiple three-state inferences
driving the inout signal. Rather than choosing one three-state to place in the IOB,
Express will place all the three-state using internal TBUFs then use a standard
OBUF at the IOB. Examine your HDL to be sure the bidirectional structure is explicit.
AR# 5405
日付 08/11/2003
ステータス アーカイブ
種類 一般