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AR# 54136

Parallel Cable IV/Vivado - The Parallel Cable IV is not supported in the Vivado tools. Can I use ChipScope Debug cores in a Vivado design?

説明

The Parallel Cable IV is not supported in the Vivado tools. If I do not have an alternative cable to use, this means that I cannot access and use any debug cores that I add to my design in Vivado logic analyzer or Vivado serial I/O analyzer.

If designing in the Vivado tools, is there any way that I can add debug cores and use the Parallel Cable IV?

ソリューション

The Parallel Cable IV will not be supported in the Vivado tools. However, ChipScope analyzer supports this cable.

To work around this issue, you must ensure that you have the correct core versions as the Vivado debug cores.

You can match the core version to run time tools by using the following:

Debug IP Core and Version
Run-time Tool Requirement
AXI ChipScope Monitor, v3.05a (or earlier) ChipScope Pro analyzer
Integrated Controller (ICON), v1.06a (or earlier) ChipScope Pro analyzer
Integrated Logic Analyzer (ILA), v1.05a (or earlier) ChipScope Pro analyzer
Integrated Logic Analyzer (ILA), v2.0 (or later) Vivado logic analyzer
Virtual Input/Output (VIO), v1.05a (or earlier) ChipScope Pro analyzer
Virtual Input/Output (VIO), v2.0 (or later) Vivado logic analyzer

The same principle applies to IBERT cores:

Debug IP Core and Version
Run-time Tool Requirement
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTZ, v2.0 ChipScope Pro analyzer or Vivado serial I/O analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v3.0 (or later) Vivado serial I/O analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v2.02a ChipScope Pro analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v3.0 (or later) Vivado serial I/O analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v2.00a (or earlier) ChipScope Pro analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v3.0 (or later) Vivado serial I/O analyzer
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v2.01a (or earlier) ChipScope Pro analyzer

To work around this issue, you need to include legacy debug cores in your Vivado design by following this procedure:

  1. Instantiate ILA/VIO and ICON in HDL. Debug core insertion into the Vivado design netlist is not supported for legacy ChipScope Pro debug IP cores.
  2. Generate Cores in the CORE Generator tool.
  3. Import netlists to the Vivado tools.
  4. Add XDC constraints for cores from the Coregendirectory to constraints file.
  5. Synthesize/Implement/write_bitstream in Vivado.
  6. Connect to Cores in ChipScope analyzer with the Parallel Cable IV.

If you have some Vivado debug cores included in the design alongside your legacy debug cores added using the process above, there are some additional considerations.

  • You must instantiate an ICON core in your design that is used to connect the other legacy ChipScope Pro debug IP cores to the JTAG chain infrastructure.
  • Make sure that the ICON and dbg_hub cores do not use the same JTAG user scan chain, otherwise you will see errors during write_bitstream DRC checking. Following is an annotated screen capture showing how to change the JTAG user scan chain of the dbg_hub core:




AR# 54136
作成日 02/07/2013
最終更新日 02/07/2013
ステータス アクティブ
タイプ 一般
デバイス
  • FPGA Device Families
  • Configuration Hardware
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  • Vivado
  • ISE Design Suite
IP
  • Debug and Verification
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  • Xilinx Parallel Cable IV