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AR# 54332

Virtex-7, Vivado SIOD - GTH 2.01 fails timing using the example design

説明

If using a Vivado Serial I/O Debug (SIOD) 2.01 core for a GTH on a Virtex 7 X980T 1926-2L, timing errors are seen in the example design when the following settings are selected:

  • 1 quad (quad 217), running at 11.2 Gb/s, 32-bit data, using the quad PLL
  • QUAD 217 REFCLK1 at 175 MHz
  • Channel 0 TXUSRCLK source
  • No external system clock

ソリューション

This is a known issue and will be fixed in a future revision of the tools.
AR# 54332
作成日 02/28/2013
最終更新日 02/28/2013
ステータス アクティブ
タイプ 一般
デバイス
  • Virtex-7
ツール
  • Vivado - 2012.4
IP
  • ChipScope Pro IBERT for 7 Series GTH