This answer record contains the Release Notes and Known Issues for the AXI UART Lite and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and older tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE AXI UART Lite IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The table below provides answer records for general guidance when using the LogiCORE AXI UART Lite.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
|(Xilinx Answer 35863)||EDK, UART Lite - How do I clear a UART Lite interrupt?|
|(Xilinx Answer 35903)||12.1 EDK, UART Lite - Why do UART errors rates increase with higher baud and lower clock frequencies?|
Known and Resolved Issues
The following table provides known issues for the AXI UART Lite, starting with v2.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
There are no known issues for the Vivado 2013.4 tool.Revision History