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AR# 54541

LogiCORE IP Video Timing Controller - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

説明

This answer record contains the Release Notes and Known Issues for the Video Timing Controller LogiCORE IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.


For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):

https://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Video Timing Controller Core Page:

https://www.xilinx.com/products/intellectual-property/ef-di-vid-timing.html

ソリューション

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core
Version
Vivado Tools
Version
IP ChangelogIP PatchesStandalone Software
Driver Patches
v6.1 (Rev. 12) 2018.2 (Xilinx Answer 71212)
v6.1 (Rev. 12)2018.1(Xilinx Answer 70699)(Xilinx Answer 71145)(Xilinx Answer 71178)
v6.1 (Rev. 12)2017.4(Xilinx Answer 65570)
v6.1 (Rev. 11)2017.3(Xilinx Answer 69903)
v6.1 (Rev. 10)2016.4(Xilinx Answer 68369)
v6.1 (Rev. 9)2016.3(Xilinx Answer 68021)
v6.1 (Rev. 8)2016.2(Xilinx Answer 67345)
v6.1 (Rev. 7)2016.1(Xilinx Answer 66930)
v6.1 (Rev. 6)2015.3(Xilinx Answer 65570)
v6.1 (Rev. 5)2015.1N/A
v6.1 (Rev. 4)2014.4(Xilinx Answer 62882)
v6.1 (Rev. 3)2014.3(Xilinx Answer 62144)
v6.1 (Rev. 2)2014.2N/A
v6.1 (Rev. 1)2014.1(Xilinx Answer 59986)
v6.12013.4N/A
v6.0 (Rev. 2)2013.3N/A
v6.0 (Rev. 1)2013.2N/A
v6.02013.1N/A


Table 2 provides answer records for general guidance when using the Video Timing Controller core.

Table 2: General Guidance

Answer Record Title
(Xilinx Answer 65801)Using the VTC with the AXI Stream to Video Out for interlaced format detection
(Xilinx Answer 39413)What signals are needed for the timing to be correctly detected and regenerated?
(Xilinx Answer 47158)Why do I not see blanking signals generated when I select the blanking signal detection?
(Xilinx Answer 55248)Why do I get the following CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks, for my IP, or why do I get CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay?


Known and Resolved Issues:


The following table provides known issues for the LogiCORE IP Video Timing Controller core, starting with v6.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record TitleVersion
Found
Version
Resolved
(Xilinx Answer 71177)Why am I seeing a failure when I try to detect and transmit SD-SDI Interlace resolutions?v6.1 (Rev. 12)N/A
(Xilinx Answer 69227)How do I configure the Video Timing Controller to de-assert VBLANK as the same time as the HBLANK at the end of the last line of the frame? v 6.1N/A
(Xilinx Answer 68711)Why do I not see any VSYNC or VBLANK outputs when using constant mode with CUSTOM timing?v6.1 (Rev. 10)N/A
(Xilinx Answer 63700)Driver does not set 'Interlaced' bit in Generator Encoding Registerv6.1N/A
(Xilinx Answer 61228)field_id_out does not toggle in constant modev6.0N/A
(Xilinx Answer 61684)Why does the VTC lock signal remain asserted when the video clock is removed?v6.0N/A
(Xilinx Answer 56274)Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?v6.0v6.0 (Rev. 2)
(Xilinx Answer 56271)Why do I get a CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay' in Vivado 2013.1 or 2013.2, my clock source is from a clock mux?v6.0v6.0 (Rev. 2)
(Xilinx Answer 52215)Why does my core fail timing with a Critical Warning?v5.01.av6.0 (Rev. 2)
(Xilinx Answer 54660)When using the Video Timing Controller, Test Pattern Generator, RGB2YCrCb Color-Space Converter or YCrCb2RGB Color-Space Converter cores, why do I get an error saying that my design can not generate a bitstream?v5.01.av6.0 (Rev. 2)
(Xilinx Answer 54611)Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled?v5.01.av6.0
(Xilinx Answer 52741)Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used?v5.01.av6.0
(Xilinx Answer 52724)Why does the VTC Generation always wait for the VTC Detection to lock when both the VTC Generation and VTC Detection are enabled?v5.01.av6.0
(Xilinx Answer 55980)Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?v5.01.av6.0 (Rev. 1)


Revision History

07/09/2018Added v6.1 (Rev. 11) and v6.1 (Rev. 12) to Version Table, (Xilinx Answer 71145)
05/26/2017Added (Xilinx Answer 69227)
02/07/2017Added v6.1 (Rev. 7), v6.1 (Rev. 8), v6.1 (Rev. 9), and v6.1 (Rev. 10) to Version Table, (Xilinx Answer 68711)
03/13/2015Added v6.1 (Rev. 3), v6.1 (Rev. 4), v6.1 (Rev. 5), and v6.1 (Rev. 6) to Version Table, (Xilinx Answer 65801)
03/13/2015Added (Xilinx Answer 63700)
09/26/2014Added (Xilinx Answer 61228)
08/01/2014Added v6.0, v6.1 (Rev. 1) and v6.1 (Rev. 2) to Version Table, (Xilinx Answer 61684)
10/23/2013Added v6.0 (Rev. 2) to Version Table (Xilinx Answer 54660) and updated Known and Resolved Issues table for 2013.3.
06/19/2013Added v6.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 56271)
05/17/2013Added (Xilinx Answer 55980)
04/03/2013Initial release

 

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
56851 ザイリンクス マルチメディア、ビデオ、および画像ソリューション センター N/A N/A

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
39413 LogiCORE IP Video Timing Controller - タイミングを正しく検出し生成するために必要な信号 N/A N/A
52215 14.3/2012.2 ビデオ IP - コアのタイミングが満たされず、クリティカル警告が表示される N/A N/A
54611 LogiCORE IP Video Timing Controller v5.01.a - 検出と生成の両方がイネーブルの場合、Video Timing Controller Generator がブランキング信号に対して早くリセットされる N/A N/A
52741 Video Timing Controller (VTC) v5.01.a - AXI4-Lite インターフェイスを使用する場合、VTC の生成によって常にスタートアップに 720p の出力タイミング信号が作成される N/A N/A
52724 LogiCORE IP Video Timing Controller (VTC) v5.01.a - VTC の生成および検出の両方が有効な場合、VTC 生成は常に VTC 検出がロックするまで待機する N/A N/A
55248 Vivado タイミング制約と IP 制約 - IP に「CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks」または「CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay」というクリティカル警告が表示される N/A N/A
55980 LogiCORE Video Timing Controller v5.01.a - AXI4-Stream のクロック周波数と AXI4-Lite インターフェイスのクロック周波数が異なると、AXI4-Lite バスでの書き込みがエラーになる N/A N/A
56271 LogiCORE IP Video Timing Controller v6.0 - クロックのソースがクロック マルチプレクサーの場合、Vivado 2013.1 または 2013.2 で「CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay'」という警告メッセージが表示される N/A N/A
56274 Vivado 2013.2 マルチメディア ビデオおよび画像処理 - Video IP に制約を設定する方法 N/A N/A
59291 LogiCORE DisplayPort - DisplayPort Source DPCD の Main Stream Attributes レジスタとユーザー データ インターフェイスに入力されるビデオのタイミングを一致させる必要があるか N/A N/A
59461 LogiCORE IP Video Deinterlacer v3.00.a - ビデオ入力に割り込みがあると Video Deinterlacer が停止することがある N/A N/A
61684 LogiCORE IP Video Timing Controller v6.0 - ビデオ クロックが失われると VTC ロック信号がアサートされたままになる N/A N/A
61228 LogiCORE IP Video Timing Controller v6.1 - field_id_out が定数モードでトグルしない N/A N/A
68711 LogiCORE IP Video Timing Controller v6.1 (Rev. 10) - CUSTOM タイミングを用いた定数モードを使用すると VSYNC または VBLANK 出力が表示されない N/A N/A
69227 LogiCORE IP Video Timing Controller v6.1 - フレームの最終ラインの最後で HBLANK と同時に VBLANK をディアサートするために Video Timing Controller をコンフィギュレーションする方法 N/A N/A
71145 2018.1 - LogiCORE IP Video Timing Controller v6.1 (Rev. 12) - LogiCORE IP Video Timing Controller v6.1 (Rev. 12) のパッチ アップデート N/A N/A
71178 2018.1 - LogiCORE IP Video Timing Controller Software Driver v7.2 - LogiCORE IP Video Timing Controller Software Driver v7.2 のパッチ N/A N/A
71176 2018.1 - Video Common Software Driver v4.3 - Video Common Software Driver v4.3 パッチ ダウンロード N/A N/A
71180 2018.1 - SMPTE UHD-SDI Transmitter Subsystem Software Driver v2.0 - SMPTE UHD-SDI Transmitter Subsystem Software Driver v2.0 のパッチ N/A N/A
71177 SMPTE UHD-SDI Transmitter / Receiver Subsystem - ​SD-SDI Interlace の解像度を検出および送信できない N/A N/A

関連アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
32754 LogiCORE IP Video Timing Controller - Release Notes and Known Issues N/A N/A
AR# 54541
日付 07/09/2018
ステータス アクティブ
種類 リリース ノート
ツール
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
IP
  • Video Timing Controller
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