This answer record contains the Release Notes and Known Issues for the SMPTE UHD-SDI Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2015.1 and later versions.
SMPTE UHD-SDI LogiCORE IP Page:
https://www.xilinx.com/products/intellectual-property/uhd-serial-digital-interface.html
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version | IP Change log | IP Patches |
|---|---|---|---|
| v1.0 (Rev. 7) | 2020.1 | (Xilinx Answer 73626) | |
| v1.0 (Rev. 7) | 2019.2 | (Xilinx Answer 72923) | |
| v1.0 (Rev. 7) | 2019.1 | (Xilinx Answer 72242) | |
| v1.0 (Rev. 6) | 2018.3 | (Xilinx Answer 71806) | |
| v1.0 (Rev . 5) | 2018.2 | No Change | (Xilinx Answer 71286) |
| v1.0 (Rev . 5) | 2018.1 | No Change | |
| v1.0 (Rev. 5) | 2017.3 | (Xilinx Answer 69903) | |
| v1.0 (Rev. 4) | 2017.1 | (Xilinx Answer 69055) | |
| v1.0 (Rev. 3) | 2016.3 | (Xilinx Answer 68021) | (Xilinx Answer 68741) |
| v1.0 (Rev. 2) | 2016.1 | (Xilinx Answer 66930) | |
| v1.0 (Rev. 1) | 2015.3 | (Xilinx Answer 65570) | |
| v1.0 | 2015.1 |
General Guidance
The table below provides Answer Records for general guidance when using the SMPTE UHD-SDI core.
| Article Number | Article Title |
|---|---|
| (Xilinx Answer 72449) | UltraScale+ GTH/GTY - Why do I see link errors on the TX when using QPLL0 and QPLL1 to switch line rates on the RX between 11.88 Gbps and 11.88/1.001 Gbps? |
| (Xilinx Answer 62645) | Can non-standard resolutions be supported? |
| (Xilinx Answer 65953) | How do I map RGB data to the SMPTE SD/HD/3G-SDI Core? |
Known and Resolved Issues
The following table provides known issues for the SMPTE UHD-SDI core, starting with v1.0, initially released in Vivado 2015.1.
Note: The "Version Found" column lists the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 73470) | An erroneous TRS pattern is generated when 128 channel audio is enabled. | v1.0 (Rev 5) | N/A |
| (Xilinx Answer 71351) | ST352 payload ID packets are only inserted on odd data streams (Y Channel) for 12-SDI mode | v1.0 (Rev 5) | v1.0 (Rev 6) |
| (Xilinx Answer 67862) | Why am I not able to properly detect 1920x1080 at 40/48fps (either 3G or 6G) or 3840x2160 at 48fps (12G) inputs? | v1.0 (Rev. 2) | v1.0 (Rev. 3) |
| (Xilinx Answer 68754) | Why do rx_mode_locked and rx_t_locked keep toggling when an SDI cable is not connected | v1.0 (Rev. 3) | v1.0 (Rev. 4) |
| (Xilinx Answer 68794) | UHD-SDI core shows Timing Errors on EDH TX paths | v1.0 (Rev. 3) | v1.0 (Rev. 4) |
| (Xilinx Answer 67742) | XAPP1248 - Synthesis of the UHD-SDI core in 2016.2 is preventing the receiver from locking to the incoming video | N/A | N/A |
| (Xilinx Answer 66734) | Why can I not target a Virtex UltraScale part with GTHs? | v1.0 | v1.0 (Rev. 2) |
| (Xilinx Answer 56449) | rx_locked occasionally asserting when no SDI cable is connected | v1.0 |
Revision History:
| 04/21/2020 | Added (Xilinx Answer 73470) |
| 06/25/2019 | Added (Xilinx Answer 72449) |
| 05/15/2019 | Added v.1.0 (Rev. 6) and v1.0 (Rev. 7) to Version Table |
| 07/20/2018 | Added (Xilinx Answer 71351) |
| 05/01/2018 | Added (Xilinx Answer 62645) |
| 04/04/2018 | Added v1.0 (Rev. 3), v1.0 (Rev. 4) and v1.0 (Rev. 5) to Version Table and (Xilinx Answer 67862) |
| 08/24/2016 | Added (Xilinx Answer 67742) |
| 06/22/2016 | Added (Xilinx Answer 56449) and (Xilinx Answer 65953) |
| 04/06/2016 | Added (Xilinx Answer 66734) and added v1.0 (Rev. 1) and v1.0 (Rev. 2) to Version Table |
| Answer Number | アンサータイトル | 問題の発生したバージョン | 修正バージョン |
|---|---|---|---|
| 56852 | ザイリンクス マルチメディア、ビデオ、および画像ソリューション センター - 主な問題 | N/A | N/A |
| 68794 | LogiCORE IP SMPTE UHD-SDI v1.0 (Rev. 3) 2016.4 - UHD-SDI コアの EDH TX パスでタイミング エラーが発生する | N/A | N/A |
| AR# 54547 | |
|---|---|
| 日付 | 08/01/2020 |
| ステータス | アクティブ |
| 種類 | リリース ノート |
| IP | |