AR# 54666


LogiCORE IP XAUI - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the XAUI Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
The last supported Vivado release of the XAUI core is version 12.3 (Rev. 6) in Vivado 2019.1.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE XAUI Core IP Page:


General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v12.6 (Rev. 6)2019.1
v12.3 (Rev. 5)2018.3
v12.3 (Rev. 4)2018.2
v12.3 (Rev. 3)2018.1
v12.3 (Rev. 2)2017.4
v12.3 (Rev. 1)2017.3
v12.3 2017.2
v12.2 (Rev. 8)2017.1
v12.2 (Rev. 7)2016.4
v12.2 (Rev. 6)2016.3
v12.2 (Rev. 5)2016.2
v12.2 (Rev. 4)2016.1
v12.2 (Rev. 3)2015.4
v12.2 (Rev. 2)2015.3
v12.2 (Rev. 1)2015.2
v12.1 (Rev. 4)2014.4
v12.1 (Rev. 3)2014.3
v12.1 (Rev. 2)2014.2
v12.1 (Rev. 1)2014.1
v11.0 (Rev. 1)2013.2

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE XAUI core.

Answer RecordTitle
(Xilinx Answer 38279)Ethernet IP Solution Center
(Xilinx Answer 33596)XAUI Frequently Asked Questions (FAQ)
(Xilinx Answer 55077)Ethernet IP Cores - Design Hierarchy in Vivado

Known and Resolved Issues

The following table provides known issues for the XAUI core, starting with v11.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 71454)This core is being deprecated and will no longer be available starting in Vivado 2019.2v12.6 (Rev. 6)NA
(Xilinx Answer 66941)DXAUI Core Example Design fails in Simulationv12.2(Rev.2)v12.2(Rev.3)
 UltraScale - GTRXRESET required after entering or exiting GT Near-end PMA loopbackv12.0v12.2
(Xilinx Answer 62354)GTRXRESET toggles when using transceiver debug PRBS inputsv12.0v12.2
(Xilinx Answer 62351)GTP and GTH - Simulation not supported with Unifast model or SIM_GTRESET_SPEEDUPv10.4NA
(Xilinx Answer 59912)Additional XDC constraints for the MDIO signal inputs to ease timing closurev12.1v12.1 (Rev. 1)
(Xilinx Answer 59292)TX Phase Alignment statemachine not reset on falling edge of powerdownv12.0v12.1 (Rev. 1)
(Xilinx Answer 59861)GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recoverv12.0v12.1 (Rev. 1)
(Xilinx Answer 59860)7 Series GTP/GTH - Update to hold off further resets to GTs during reset_in_progressv12.0v12.1 (Rev. 1)
(Xilinx Answer 58083)Update to 7 Series GTX Transceiver attribute - RXDFEXYDENv10.4v12.0
(Xilinx Answer 56312)Update to 7 Series GTP/GTH reset logicv11.0 (Rev. 1)v12.0
(Xilinx Answer 55132)Artix-7 - 20G DXAUI - Marginal timing seenv11.0Work-around in Answer Record
(Xilinx Answer 55837)Update to RX termination for 7 Series GTP and GTHv11.0v11.0 (Rev. 1)
(Xilinx Answer 55226)Critical Warning - No cells match DRP path for false path constraintv11.0v11.0 (Rev. 1)
(Xilinx Answer 55009)7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Modev10.4v11.0
(Xilinx Answer 53779)Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Siliconv10.4v11.0
(Xilinx Answer 53561)Artix-7 - RX Reset Sequence Requirement for Production Siliconv10.4v11.0
(Xilinx Answer 50848)7 Series GT Transceivers - Reset maybe needed after disabling Loopbackv10.3v11.0
(Xilinx Answer 50795)7 Series - Timing failures might occur in XAUI Example Designv10.4v11.0


アンサー レコード リファレンス

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
55226 LogiCORE XAUI v11.0 - Vivado - フォルス パス制約の DRP パスに一致するセルがないというクリティカル警告が発生する N/A N/A
55132 LogiCORE XAUI v11.0 - Vivado - Artix-7 - 20G DXAUI - 限界タイミング エラー N/A N/A
55077 Ethernet IP - Vivado ツールのデザイン階層 N/A N/A
58083 RXAUI v3.0 および XAUI v11.0 以前のバージョン - 7 シリーズ GTX トランシーバーの属性 RXDFEXYDEN のアップデート N/A N/A
59860 XAUI v12.0 および RXAUI v4.0、Vivado 2013.4 およびそれ以前 - reset_in_progress 中に GT への追加リセットを回避するためのアップデート N/A N/A
59861 XAUI および RXAUI - Vivado 2013.4 以前 - GTP および GTH - プロダクション リセット DRP シーケンスが停止し、リコンフィギュレーションが必要になる N/A N/A
59292 XAUI/RXAUI Vivado 2013.4 およびそれ以前のバージョン - TX 位相アライメント ステートマシンがパワーダウンの立ち下がりエッジでリセットされない N/A N/A
59912 XAUI v12.1 - MDIO 信号入力に XDC 制約を追加するとタイミング クロージャが容易になる N/A N/A
62351 XAUI および RXAUI - GTP および GTH - DRP プロダクション リセット シーケンスを使用する場合、Unifast モデルまたは SIM_GTRESET_SPEEDUP を使用するシミュレーションはサポートされていない N/A N/A

関連アンサー レコード

AR# 54666
日付 12/09/2020
ステータス アクティブ
種類 リリース ノート
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