AR# 54673

MIG 7 Series DDR3 - デバッグ信号が有効になっていると ChipScope Write ILA のライト レベリング デバッグ信号が正しく接続されない

説明

問題の発生したバージョン : MIG 7 Series 1.8
修正バージョン : (ザイリンクス アンサー 45195) を参照

デバッグ信号を有効にして MIG 7 Series DDR3 デザインを生成すると、ライト レベリング キャリブレーションのデバッグ信号の一部が Write ILA ChipScope コアに正しく接続されません。 

正しく接続されていない信号は次のとおりです。

  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
    and 
  • wl_edge_detect_valid_r. 

このアンサーでは、今後の MIG 7 Series で問題が修正されるまで、これらの ILA 接続を手動で修正する方法を示します。

ソリューション

user_design/rtl/core_name.v モジュールでは、デバッグ信号が ChipScope ILA コアへ接続されています。

このモジュールを開いて「ILA for monitoring write path signals」セクションの位置を特定します。

次のように、接続を更新します。

コメント部分のポート番号が古く、誤った接続です。
 
//*******************************************************
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   //*******************************************************
 
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
 
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129
 

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
14298 ケーブル - パラレル ケーブル III の仕様および寸法 N/A N/A
14299 8.1i Virtex-4 MAP - "ERROR:Pack:1118 - The symbol U2/SRL16E was unable to be implemented in a slice containing no other symbols..." N/A N/A
14297 ケーブル - パラレル ケーブル IV の仕様および寸法 N/A N/A
N/A N/A
14359 7.1i XST - How do I pass the STEPPING attribute through HDL in XST? N/A N/A
14350 9.1i NGDBuild/Constraint - "WARNING:Ngd:231 - PERIOD TIMESPEC '%s' has TIMEGRP '%s' which contains a mixture of PADs and synchronous elements..." N/A N/A
1435 Invoking XDM requires to be logged in as root N/A N/A
14458 Virtex-II/-II Pro Configuration - BUSY asserts during SelectMAP configuration with a DES encrypted bitstream N/A N/A
14456 System ACE CF - The ERROR LED turns on when configuring devices with a CF Card N/A N/A
N/A N/A
14628 5.2i CPLD Fitter CoolRunner XPLA3 - A fatal error occurs when auto-slew is used (ISE "Timing-driven slew rate" option) N/A N/A
14726 Packaging: What packages are plastic and what ones are ceramic? N/A N/A
14728 5.1i PACE - When I place a group on an insufficient location range, the out-of-range group members are not placed N/A N/A
1472 XC3000: I/O Slew Rates and other AC parameters (rise/fall times) N/A N/A
140 XC4000: weight of 4005CB164 in Military B package - 11.5 grams N/A N/A
14594 4.2i SP2 iMPACT - Configuration from the System ACE MPM device fails when bit stream compression is used N/A N/A
1459 How to get the pin order of a XSI Library Cell in Synopsys or How to get the pins names for a XSI library cell N/A N/A
1469 *Obselete* xchecker N/A N/A
14756 4.2i iMPACT - iMPACT does not allow a System ACE soft-controller (SC) solution without an XC18V01 N/A N/A
14753 4.2i iMPACT - When I use the verify command line option in batch "File Generation" mode, incorrect TDO values are written to the SVF file N/A N/A
14752 4.2i/5.2i iMPACT - The "verify" operation for FPGA devices is not supported in SVF mode N/A N/A
N/A N/A
14857 5.1i CORE Generator - Known Issues for CORE Generator in the 5.1i software release N/A N/A
1485 Foundation XVHDL: Using RAM and ROM in XC4000 devices N/A N/A
14220 LogiCORE - Twos Complementer Core: Why is the output width created equal to (input width + 1)? N/A N/A
14226 4.2 ISE Integration Synplify/Synplify Pro - 9500 and Coolrunner does not work through the ISE GUI. N/A N/A
N/A N/A
1432 HARDWARE DEBUGGER: Many internal signals cannot be selected N/A N/A
14967 Virtex-II packaging - What does the NC (No Connect) mean? Can I use these pads for any purpose? N/A N/A
1416 CHECK or XNFPREP fail because of invalid characters in signal names N/A N/A
14468 BitGen - 出力ファイルの説明 (.bit、.rbt、.bgn、.drc、msk、.ll、.nky、.rba、.rbb、.rbd、.msd、.bin) N/A N/A
N/A N/A
1473 Foundation XVHDL: How to control the # of BUFGs which are automatically inserted. N/A N/A
14833 5.2i CORE Generator - Async FIFO v4.0 : Empty flag fails to go high using VCS simulator N/A N/A
1483 FPGA Express: How do you specify slew rate in FPGA Express? N/A N/A
14564 CORE Generator, Gigabit Ethernet MAC v2.0 - MGTs do not work properly in the PCS/PMA configuration of the core N/A N/A
1456 HardWire: XNFRPT -I N/A N/A
1486 Foundation XVHDL: Using CLB Latches N/A N/A
N/A N/A
14333 XST - "ERROR:HDLParsers:1400 - .vhd Line xx. is not the name of a procedure" N/A N/A
N/A N/A
14432 4.2i Install - I installed my 4.2i Foundation Express product and I can't target Virtex-II XC2V500-1500 devices. N/A N/A
N/A N/A
14971 Virtex-II Pro RocketIO - Can BREFCLK and RXRECCLK drive FPGA internal logic? N/A N/A
14978 Virtex-II Pro RocketIO - RocketIO トランシーバーに使用可能なコネクタ N/A N/A
N/A N/A
14174 4.2i CORE Generator - Known Issues in the 4.2i IP Update #2 (E_IP2). N/A N/A
1417 Programmers: HW-130: Are the HW-112 (PP2) adapters compatible with the HW-130 Programmer? N/A N/A
14271 4.2i CORE Generator - Installation Instructions for 4.2i IP Update #2 (E_IP2) N/A N/A
N/A N/A
14603 SIMULATION, DCM - CLKDV output aligns with the falling edge of CLK0 instead of the rising edge of CLK0 N/A N/A
14608 Virtex-II Pro RocketIO - Gigabit Ethernet interoperability has been verified N/A N/A
14606 Virtex-II Pro RocketIO - How do I perform clock correction on a multiple comma sequence (rather than a single comma)? N/A N/A
N/A N/A
14702 4.2i IBISWriter - In XC4000 models, the "minimum" and "typical" values for the package parasitic data are switched N/A N/A
14708 4.2i Foundation Schematic Editor - automatically makes use of I/O pins to connect macros in schematics N/A N/A
N/A N/A
143 *Obsolete* JTAG - What is the state of the INIT pin during boundary scan configuration? N/A N/A
1484 Foundation XVHDL: Using XBLOX N/A N/A
14946 LogiCORE RapidIO - Is an evaluation model of the RapidIO Core available? N/A N/A
1494 XC4000E/EX/XL/XV/XLT: Duty Cycle N/A N/A
14031 XST - "ERROR:HDLParsers:3017 - .vhd: Library unit pkg_name in library was compiled before unit that it uses" N/A N/A
N/A N/A
14574 AFX - Xilinx Prototyping and Demonstration Board CD: "Error: The 'input' port 'USER_RESET on demo.v file is incompatibly declared as 'reg'." N/A N/A
N/A N/A
14670 MicroBlaze, OPB Peripherals - Improving decode time by increasing address spacing for OPB Peripherals N/A N/A
N/A N/A
14146 4.2i Virtex-II, BitGen - The 2V4000 DCM may require a BitGen option for high CLKIN frequency N/A N/A
N/A N/A
14202 LogiCORE Distributed Arithmetic FIR (DA FIR), MAC FIR, DDC - Why are output values for an invalid parameter error reported in a different base format than the input? N/A N/A
1420 SPROMS - Can the VPP/VCC pin be tied through a resistor to +5V? N/A N/A
14306 *Obsolete* 4.1i iMPACT - "ERROR:Portability:90 - Command line error: Argument[2]...'/dev/ttya'" N/A N/A
14305 XST - "WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming to 1" N/A N/A
1430 ORCAD - DS32-VST- "ERROR-030, Symbol has incomplete pin information." N/A N/A
N/A N/A
14281 LogiCORE Gigabit Ethernet MAC - Is the LLC/SNAP protocol supported? N/A N/A
14287 CORE Generator Gigabit Ethernet MAC - The receiver byte count is 4 bytes higher than expected when I calculate my own CRC N/A N/A
14386 XST- A design does not fit a CPLD when I synthesize with XST, but it fits easily with another synthesis tool N/A N/A
14382 4.1i XST - "ERROR:Xst:765 - file_name.vhd (Line xx). Component 'comp_name' has same name as enclosing entity." N/A N/A
N/A N/A
14541 8.1i - "ERROR:Place:1827 - There are special SelectI/O banking requirements for the package being targeted..." N/A N/A
XC5200: LCA2XNF v5.2.1 writes out 5-input logic gates for XC5200 N/A N/A
14719 パラレル ケーブル IV - TMS および TDI でパラレル ケーブル IV が提供するセットアップ タイム、およびケーブルの TDO ピンに必要なセットアップ要件 N/A N/A
N/A N/A
14810 10.1 Floorplanner - I cannot drag-and-drop (place) my RPM component from the Hierarchy window to the Edit window N/A N/A
14811 Databook - What tests are conducted on Xilinx devices before the devices are qualified? N/A N/A
14959 5.1isp1 DCM Wizard - Choosing "Local Routing" for the global buffer does not cause the clock signal to be brought out to the entity port N/A N/A
14950 5.1i iMPACT - The addition of a third-party (non-Xilinx) BSDL file results in a Dr. Watson access violation N/A N/A
14955 8.1i Spartan-IIE PAR - An incorrect DRC check of DLL connectivity causes an invalid error (ERROR:Place:110) N/A N/A
14953 Virtex-II Pro RocketIO - Is it possible for channel bonding to be performed across multiple Virtex-II Pro chips? N/A N/A
1495 M1 and Workview Office: How do I set up concurrent licensing? N/A N/A
N/A N/A
14683 10.0 PACE - When I move my cursor over an assigned pin in the package view, the pin name does not appear (Japanese version) N/A N/A
14685 4.2i Project Navigator - Design Consistency Check - This design contains sources that are not supported N/A N/A
1468 XBLOX 5.x: Possible simulation problems if the labels are missing N/A N/A
14781 v2.0 CORE Generator Gigabit Ethernet MAC - Which features are optional, and which are configurable? N/A N/A
N/A N/A
14158 LogiCORE Ten Gigabit Ethernet MAC v2.0 - Resource utilization/slice counts N/A N/A
N/A N/A
N/A N/A
AR# 54673
日付 08/18/2014
ステータス アクティブ
種類 既知の問題
デバイス
IP