AR# 54673


MIG 7 Series DDR3 - デバッグ信号が有効になっていると ChipScope Write ILA のライト レベリング デバッグ信号が正しく接続されない


問題の発生したバージョン : MIG 7 Series 1.8
修正バージョン : (ザイリンクス アンサー 45195) を参照

デバッグ信号を有効にして MIG 7 Series DDR3 デザインを生成すると、ライト レベリング キャリブレーションのデバッグ信号の一部が Write ILA ChipScope コアに正しく接続されません。 


  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
  • wl_edge_detect_valid_r. 

このアンサーでは、今後の MIG 7 Series で問題が修正されるまで、これらの ILA 接続を手動で修正する方法を示します。


user_design/rtl/core_name.v モジュールでは、デバッグ信号が ChipScope ILA コアへ接続されています。

このモジュールを開いて「ILA for monitoring write path signals」セクションの位置を特定します。


   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
3066 96 DATA BOOK: XC3064A/L, XC3164A/L, XC3O90A/L, XC3190A/L I/O pins misprint N/A N/A
3076 Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed away or tied to VCC/GND. N/A N/A
3002 Foundation F1.x Project Manager: Very slow when launching under Win95 N/A N/A
30120 Endpoint Block Plus Wrapper for PCI Express v1.6 および v1.6.1 - ISE 10.1 初期 IP 3 (IP_10.1.0) のリリース ノートおよび既知の問題 N/A N/A
30092 System Generator for DSP - How do I install the plugin for the XtremeDSP Development Board Spartan-3A DSP Edition and the Spartan-3A DSP Video Starter Kit? N/A N/A
30090 Virtex-5 System Monitor - DRP での DENの動作 N/A N/A
30091 9.2i MAP - SmartGuide: "FATAL_ERROR:Pack:pksbashapemerge.c:259:" N/A N/A
30096 9.2i iMPACT - "ERROR: iMPACT:583" for XC4VFX40 devices N/A N/A
3009 2.1i Design Manager - Core dumps when using Exceed/W N/A N/A
30151 LogiCORE Fibre Channel Arbitrated Loop v2.3 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0) N/A N/A
30150 LogiCORE Fibre Channel v3.3 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0) N/A N/A
30813 10.1 UniSim/SimPrim-: # Warning : Address DADDR=1010110 is unsupported at DCM_ADV N/A N/A
30810 LogiCORE Multiplier v10.1 - Why are the Block Memory resource estimations in accurate for my contact-coefficient multiplier with a large constant, and the large A input? N/A N/A
30535 10.1 CORE Generator - FIR Compiler v3.2 のグラフのテキストが消える N/A N/A
30539 10.1 Floorplan Editor - Floorplan Editor uses old date when UCFs are added/removed from project N/A N/A
30637 11.1 EDK - My 3rd-party RTOS seems to have sub-optimal performance on the PPC440 in Virtex-5 FPGA N/A N/A
30896 10.1 Constraints Editor - Creating a "pad to setup" constraint crashes ISE N/A N/A
30894 10.1 Constraint Editor - Cannot create Net TING constraint without referencing a TIMER N/A N/A
30895 10.1 Constraints Editor - Double clicking on pad-to-setup windows does not work N/A N/A
30893 10.1 Constraint Editor crashes when disabling / enabling constraints N/A N/A
30891 10.1 ISE - Project Navigator (_pn.exe) crashes on startup using Windows Vista Business Service Pack 1 64-bit N/A N/A
30958 Virtex-5 GTX RocketIO SIS キット - MGTAVTTX であるはずの GTX REFCLK 電源が MGTAVCCPLL とラベルされる N/A N/A
30953 Virtex-5 GTX RocketIO - DFE クロック遅延キャリブレーション上書き N/A N/A
30954 Virtex-5 GTX RocketIO Wizard v1.4 - Release Notes and Known Issues for ISE 10.1 IP Update 2 (IP_10.1.2) N/A N/A
30951 Virtex-4 GT11 RocketIO - Reducing receive inter-lane skew through use of RXSYNC for channel bonded applications. N/A N/A
30362 10.1 PACE : スピード グレードが -4Q の Spartan-IIE または Spartan-3E/-3A デバイスを読み込むことができない N/A N/A
30360 10.1 Floorplanner - Crashes when the cursor is placed over an assigned pin N/A N/A
30361 10.1 Floorplan Editor - IOStandard を変更できない N/A N/A
30369 10.1 Constraint System - Lack of error numbers and UCF line numbers for constraint syntax issues N/A N/A
30366 10.1 Floorplan Editor - Spartan-3、Spartan-3A、Spartan-3AN、Spartan-3A DSP デバイス用の Vref ピンすべてと右側の I/O ピンが表示されない N/A N/A
30364 10.1 Constraints Editor - Unable to create constraints for EDIF project N/A N/A
3036 M1.3 Map - Map will not push buffer (or logic optimized to buffer) forward into closed FMAP (MAP=PUC or PLC) N/A N/A
30778 10.1 EDK - 「ERROR: Could not find BestRun in system_xplorer.rpt」というエラー メッセージが表示される N/A N/A
3013 FPGA Express 1.2/Foundation 1.3: Creating HDL Macros with FPGA Express 1.2 for Placement on a Foundation 1.3 Top-Level Schematic N/A N/A
30233 10.1 Floorplan Editor - New UCF gives HierarchicalDesignC:124 error on save N/A N/A
3023 Foundation State Editor: How to modify encoding scheme for State Machines (ie, one-hot)? N/A N/A
30821 ChipScope Pro - Analyzer always opens ChipScope bin directory as default search path N/A N/A
30829 10.1 ChipScope Pro - When using the IBERT parameter sweep console, I receive "Error on get Sweep Test Result file" and some of my results are missing N/A N/A
30822 10.1 ChipScope Pro IBERT - IBERT コアでの Virtex-5 SX240T のサポート N/A N/A
30827 10.1 ChipScope Pro - Cannot launch Agilent Serial Link Optimizer from the Analyzer GUI N/A N/A
30828 10.1 ChipScope Pro IBERT - When I use the Parameter Sweep feature, the ".csv" file misnumbers the first iteration and skips the last iterations N/A N/A
30825 10.1 ChipScope Pro Analyzer - Changing a VIO output type from "text" to "toggle" also changes the value N/A N/A
30826 10.1 ChipScope Pro - The Analyzer IBERT console "Edit Ports" dialog tab is incorrectly labeled "Attribute name" N/A N/A
30823 10.1 ChipScope Pro IBERT - Change to the GTP/GTX RX Coupling description N/A N/A
30824 10.1 ChipScope Pro - In the Analyzer GUI, the closing "x" in Configure Dialog does not work N/A N/A
3082 CPLD : XC9500: obtaining Fcnt (operating freq for 16 bit counters) N/A N/A
30923 Virtex-5 - コンフィギュレーション後に SPI フラッシュにアクセスする方法 N/A N/A
30929 XtremeDSP Development Kit-IV - Why is there no timing diagram for a Single Write Transfer? N/A N/A
3092 Foundation F1.3 State Editor: when selecting HOLD for Unsatisfied Conditions, selection not kept. N/A N/A
30401 LogiCORE Block Memory Generator v2.7 - GUI crashes with certain Write Depth and Write Width values N/A N/A
3040 3.1i CORE Generator - Sample COREGen .coe coefficient files for a PDA FIR filter, RAM and ROM. N/A N/A
30502 10.1 Timing Anlaysis - Can you TIG the path from the Tristate of IOB to input? N/A N/A
30503 11.1 Known Issue, Timing Analyzer - Multiple UCF files do not show up in Timing Analyzer N/A N/A
30508 10.1 Timing Analyzer - Timing Analyzer does not notify me when it is out of sync with UCF changes N/A N/A
30501 System Generator for DSP - Error "Unable to load model file.." occurs when trying to open mdl file N/A N/A
30506 11.1 Known Issue - Timing Analyzer - Timing Analyzer fails to open Constraint Editor for a design with multiple UCF files N/A N/A
30507 10.1 Constraints Editor - Does not show available block RAM FIFOs of FFs in "Group by Element Type" Dialog N/A N/A
30504 10.1 Constraints Editor - I/O timing wizard displays a black window N/A N/A
30505 10.1 Timing Analyzer - Closing Timing Analyzer produces temporary file names for unsaved reports N/A N/A
30647 LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 - Virtex-5 GTX VCS Verilog functional and timing simulation errors out and does not complete N/A N/A
30646 10.1 SimPrims - X_IDELAY の出力が VCS Verilog シミュレーションで X (不明) となる N/A N/A
30642 10.1 EDK - Why does the chipscope_icon_v1.02a use BUFGs even though I set use_bufg = false? N/A N/A
3064 M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL. N/A N/A
30373 ISE - Issues with Microsoft Windows Vista User Access Control (UAC) N/A N/A
30371 10.1 Floorplan Editor - Area Group ranges are incorrectly written N/A N/A
30372 12.1 Install - 32-bit cable drivers do not work on a 64-bit operating system N/A N/A
30370 10.1 Constraints Editor - OFFSET IN (Clock to Setup) Wizard does not provide "ns" as valid values N/A N/A
3037 M1 PLD_EDIF2SIM, PLD_XNF2SIM, PLD_EDIF2TIM - "Error: Could Not find the External part "$SIMPRIMS/___"" N/A N/A
30470 10.1 Timing Analyzer - The tool complains about constraint lines that no longer exist in source UCF N/A N/A
30007 Install - "This program might not have installed correctly" message occurs at the end of Xilinx software installation on Vista N/A N/A
30008 9.2.01 System Generator for DSP - Why do I receive errors when I use the custom compilation targets from System Generator examples folder as described by "Creating Compilation Targets" in the help? N/A N/A
30006 9.2i EDK, MPMC v3.00b - ERROR:LIT:297 - BUFG or BUFGCTRL are the only valid components that can drive REFCLK pin N/A N/A
3000 CPLD XC9500 Family - Why do the XC9500 family libraries have pull-up elements? N/A N/A
30109 9.2i EDK - Create/Import Peripheral Wizard (CIP) - HDL Parser errors detected N/A N/A
30106 Spartan-3A/-3AN/-3A DSP - BSDL design warnings might not be in the .bsd file N/A N/A
3010 FPGA Express: Instantiating an EDIF from a Foundation Schematic into a top-level FPGA Express Verilog or VHDL Design N/A N/A
3024 DATA BOOK: Timing data applied to Commercial, Industrial, and Military devices N/A N/A
3034 Foundation Simulator: How to print a specific range of the simulation waveform N/A N/A
3007 XABEL, Foundation 3.1i - The AHDL2BLF or BLIFOPT step runs indefinitely during the ABL2EDIF process N/A N/A
30939 LogiCORE Serial RapidIO v4.3 - Core LCSBA implementation removes 64 MB of possible addressing space N/A N/A
30930 ChipScope Pro Virtex-5 SIOTK - PMA_RX_CFG default setting N/A N/A
30936 12.1 ISE - XST、NGDBuild などを実行すると複数のプロセスが起動する N/A N/A
30452 10.1 EDK - Error: "xps_iic INSTANCE: - /proj/dir/my_proj/system.mhs line 85 - could not find the MPD!" N/A N/A
30450 10.1 iMPACT - When generating an SVF for an XCFxxP PROM, following message occurs: "The operation did not complete successfully" N/A N/A
30458 Synplify - Virtex-5 FXT デバイスをサポートするバージョン N/A N/A
30510 9.2.01 - System Generator for DSP - What happened to the virtual platform option that allowed me to simulate my EDK Processor block with software in System Generator? N/A N/A
30612 9.2i - iMPACT - Shows warning message while generating the SPI PROM file for Automotive Spartan-3E devices N/A N/A
30878 13.1 EDK - CPU リセット後ソフトウェア アプリケーションが正しく動作しない N/A N/A
AR# 54673
日付 08/18/2014
ステータス アクティブ
種類 既知の問題
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