UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5516

1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.

説明

The bitstream for the xc4000XL(A) and SpartanXL IFD with a clock enable
is incorrect. The problem is that the IFD is clocking the new data in when
the enable is inactive. The problem seems to be that the clock enable
mux is using the feedback from the master latch instead of the slave latch.

ソリューション

A fix for this problem is available in the 1.5i Service Pack2:

(Xilinx Solution #5887)


AR# 5516
日付 04/19/2000
ステータス アーカイブ
種類 一般
このページをブックマークに追加