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AR# 5553

1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.

説明

The symptom is the mapper produces a GCLKIOB comp whose name ("clock") collides with its output signal name. When ngdanno tries to name the top level port/signal after the IOB comp, the name collision is detected and that signal name is changed from "clock" to "clock_p". This causes the simulation problem.

signal CLOCK : STD_LOGIC;
^
**Error: vhdlan,1072 rphy.vhd(108):
Illegal redeclaration of CLOCK.
I => CLOCK_P,
^
**Error: vhdlan,575 rphy.vhd(809):
CLOCK_P is not declared.

Logical (with mapped.ngm) worked OK.

ソリューション

A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
AR# 5553
作成日 02/02/1999
最終更新日 04/10/2000
ステータス アーカイブ
タイプ 一般