説明

問題の発生したバージョン : v1.9
修正バージョン : (ザイリンクス アンサー 45195) および (ザイリンクス アンサー 54025) を参照

キャリブレーションの EDGE_ADV ステージ中に、pi_edge_adv 信号が滞り、標準操作中にデータ エラーが発生する可能性があります。

ソリューション

キャリブレーションの EDGE_ADV ステージ中に、バイト グループから取り込まれたデータが負のエッジに揃えられると、ICLKDIV 出力を 1 高速クロック サイクル分シフトさせる PHASER_IN への EDGE_ADV 入力が正のエッジにデータを調整するために使用されます。調整が必要なときは、*_read_stage2_cal.v の pi_edge_adv 信号が 1 クロック サイクル間アサートされます。場合によっては、*_read_stage2_cal.v の pi_edge_adv 信号が滞り、データ バイト エラーが発生することがあります。

この問題を回避するには、mig_7series_v1_9_rld_phy_read_stage2_cal.v で RTL を次のように変更します。

次のコードを検索します。

reg  [2:0]                           pi_edge_adv_wait_cnt;
  always @ (posedge clk) begin
         if (rst_clk) begin
             pi_edge_adv  <= #TCQ 0;
bitslip      <= #TCQ 0;
             phase_error  <= #TCQ 0;
             pi_edge_adv_wait_cnt <= #TCQ 0;
             inc_byte_cnt <= #TCQ 0;
         end else begin
    if (nCK_PER_CLK == 2) begin
               if ((clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)) begin
                 if (phase_bslip_vld_chk[byte_cnt] == 1'b1 &&
        pi_edge_adv_wait_cnt == 3'b000) begin
                    pi_edge_adv  <= #TCQ 1;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ 111;
                    inc_byte_cnt <= #TCQ 0;
                 end else if (phase_bslip_vld_chk[byte_cnt] == 1'b0 &&
                 pi_edge_adv_wait_cnt == 3'b000) begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ 111; 
                    inc_byte_cnt <= #TCQ 0;
                 end else if (pi_edge_adv_wait_cnt == 3'b010) begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                    inc_byte_cnt <= #TCQ 1;
                 end else begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                    inc_byte_cnt <= #TCQ 0;
                 end
  end //end of (clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)
end else begin //nCK_PER_CLK == 4
  //Even though we don't use the edge_adv signal we use the same
  //counter
  if (edge_adv_cal_start_r2 && (!edge_adv_cal_done)) begin
    if (phase_vld_check[byte_cnt] == 1'b1 &&
        pi_edge_adv_wait_cnt == 3'b000) begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ 111;
                   inc_byte_cnt <= #TCQ 1;
    end else if (phase_vld_check[byte_cnt] == 1'b0 &&
                 pi_edge_adv_wait_cnt == 3'b000) begin
                   bitslip      <= #TCQ 1;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ 111;
                   inc_byte_cnt <= #TCQ 0;
    end else if (pi_edge_adv_wait_cnt == 3'b010) begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                   inc_byte_cnt <= #TCQ 0;
                 end else begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                   inc_byte_cnt <= #TCQ 0;
                 end
  end
end //end of //nCK_PER_CLK == 4
         end //end of else
      end //end of always

reg  [3:0]                           pi_edge_adv_wait_cnt;
 always @ (posedge clk) begin
         if (rst_clk) begin
             pi_edge_adv  <= #TCQ 0;
bitslip      <= #TCQ 0;
             phase_error  <= #TCQ 0;
             pi_edge_adv_wait_cnt <= #TCQ 0;
             inc_byte_cnt <= #TCQ 0;
         end else begin
    if (nCK_PER_CLK == 2) begin
               if ((clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)) begin
                 if (phase_bslip_vld_chk[byte_cnt] == 1'b1 &&
        pi_edge_adv_wait_cnt == 4'b0000) begin
                    pi_edge_adv  <= #TCQ 1;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
                    inc_byte_cnt <= #TCQ 0;
                 end else if (phase_bslip_vld_chk[byte_cnt] == 1'b0 &&
                 pi_edge_adv_wait_cnt == 4'b0000) begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ 4'b1111; 
                    inc_byte_cnt <= #TCQ 0;
                 end else if (pi_edge_adv_wait_cnt == 4'b0010) begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                    inc_byte_cnt <= #TCQ 1;
                 end else begin
                    pi_edge_adv  <= #TCQ 0;
                    phase_error  <= #TCQ 0;
                    pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                    inc_byte_cnt <= #TCQ 0;
                 end
  end //end of (clkdiv_phase_cal_done_5r) && (!edge_adv_cal_done)
end else begin //nCK_PER_CLK == 4
  //Even though we don't use the edge_adv signal we use the same
  //counter
  if (edge_adv_cal_start_r2 && (!edge_adv_cal_done)) begin
    if (phase_vld_check[byte_cnt] == 1'b1 &&
        pi_edge_adv_wait_cnt == 4'b0000) begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
                   inc_byte_cnt <= #TCQ 1;
    end else if (phase_vld_check[byte_cnt] == 1'b0 &&
                 pi_edge_adv_wait_cnt == 4'b0000) begin
                   bitslip      <= #TCQ 1;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ 4'b1111;
                   inc_byte_cnt <= #TCQ 0;
    end else if (pi_edge_adv_wait_cnt == 4'b0010) begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                   inc_byte_cnt <= #TCQ 0;
                 end else begin
                   bitslip      <= #TCQ 0;
                   phase_error  <= #TCQ 0;
                   pi_edge_adv_wait_cnt <= #TCQ pi_edge_adv_wait_cnt -1 ;
                   inc_byte_cnt <= #TCQ 0;
                 end
  end
end //end of //nCK_PER_CLK == 4
         end //end of else
      end //end of always

改訂履歴
2013/05/06 - 初版

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