AR# 560: SYNPLIFY: How to infer an enable register for a tri-state (storing 'z' over multiple clock cycles)?
AR# 560
SYNPLIFY: How to infer an enable register for a tri-state (storing 'z' over multiple clock cycles)?
説明
Keywords: Synplify, Verilog, VHDL
Urgency: Standard
General Description: Synplify can not infer the enable logic for a registered tristate driver. Synplify will issue this error message:
"Storing the 'Z' value over multiple clock cycles is not supported for flop_tb."
As of version 5.0.8a and later, Synplify's HDL support has been enhanced to recognize the storage of Z (high impedance) across multiple clock cycles is now supported for both VHDL and Verilog. If you're using a version earlier than 5.0.8, please upgrade to a more recent version of Synplify from Synplicity:
However, a workaround to this problem is to explicity declare an enable signal and its logic.
ソリューション
1
VHDL ----
Example 1 Will not synthesis with versions of Synplify prior to 5.0.8 Example 2 The workaround to this problem.
Example 1 --------- library ieee; use ieee.std_logic_1164.all;
entity EXAMPLE is port (D_IN, CLK, RST, ENB : in std_logic; Q_OUT : out std_logic) ; end EXAMPLE;
architecture XILINX of EXAMPLE is
begin
process(D_IN, CLK, RST) begin if (RST = '1') then Q_OUT <= 'Z'; elsif rising_edge(CLK) then if (ENB = '1') then Q_OUT <= D_IN; else Q_OUT <= 'Z'; end if; end if; end process;
end XILINX;
Example 2 --------- library ieee; use ieee.std_logic_1164.all;
entity EXAMPLE is port (D_IN, CLK, RST, ENB : in std_logic; Q_OUT : out std_logic) ; end EXAMPLE;
architecture XILINX of EXAMPLE is
signal Q_OUT_EN, Q_OUT_REG : std_logic;
begin
Q_OUT <= Q_OUT_REG when (Q_OUT_EN = '1') else 'Z';
process(D_IN, CLK, RST) begin if (RST = '1') then Q_OUT_REG <= '0'; Q_OUT_EN <= '0'; elsif rising_edge(CLK) then Q_OUT_REG <= D_IN; Q_OUT_EN <= ENB; end if; end process;
end XILINX;
2
Verilog -------
Example 1 Will not synthesis with versions of Synplify prior to 5.0.8 Example 2 The workaround to this problem.
Example 1 --------- module EXAMPLE (D_IN, CLK, RST, ENB, Q_OUT); input D_IN, CLK, RST, ENB; output Q_OUT;
reg Q_OUT;
always @(posedge CLK or posedge RST) if (RST | !ENB) Q_OUT = 1'bz; else Q_OUT = D_IN;
endmodule
Example 2 --------- module EXAMPLE (D_IN, CLK, RST, ENB, Q_OUT); input D_IN, CLK, RST, ENB; output Q_OUT;
reg Q_OUT_EN, Q_OUT_REG;
assign Q_OUT = (Q_OUT_EN) ? Q_OUT_REG : 1'bz;
always @(posedge CLK or posedge RST) if (RST) begin Q_OUT_REG = 0; Q_OUT_EN = 0; end else begin Q_OUT_REG = D_IN; Q_OUT_EN = ENB; end