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AR# 5625

Instantiating Xilinx Library elements in Foundation 1.5xx HDL flow: where can you get interface information

説明

Keywords: Foundation, Express, VHDL, Verilog, library, macro, instantiate

Urgency: Standard

General Description:
How does one instantiate components from the Xilinx Unified Library?

ソリューション

All Xilinx primitives and most macros can be instantiated in a design to be
synthesized by FPGA Express. Use the Xilinx Libraries Guide to find the
names of the pins.

You can also refer to the port declaration in the unisim library for each
device since they conform to Xilinx Unified Library.

For example if you are targeting a virtex family in a verilog HDL flow in
foundation 1.5xx, and need to look up the interface information for
SRL16, you can refer to: %xilinx%\verilog\src\UNIVERTEX\SRL16.v
For VHDL flow you can refer to
%xilinx%\vhdl\src\unisims\unisim_VCOMP.vhd file.

For CPLD, you can alternatively refer to the "Library Component
Specifications" appendix Appendix A of
http://toolbox.xilinx.com/docsan/data/alliance/syn/syn.htm
AR# 5625
作成日 08/31/2007
最終更新日 10/05/2008
ステータス アーカイブ
タイプ 一般