General Description: How does one instantiate components from the Xilinx Unified Library?
All Xilinx primitives and most macros can be instantiated in a design to be synthesized by FPGA Express. Use the Xilinx Libraries Guide to find the names of the pins.
You can also refer to the port declaration in the unisim library for each device since they conform to Xilinx Unified Library.
For example if you are targeting a virtex family in a verilog HDL flow in foundation 1.5xx, and need to look up the interface information for SRL16, you can refer to: %xilinx%\verilog\src\UNIVERTEX\SRL16.v For VHDL flow you can refer to %xilinx%\vhdl\src\unisims\unisim_VCOMP.vhd file.