UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5682

FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design

説明

Keywords: OBUF, OBUFE, OBUFT, 9500

Urgency: Standard

General Description: After instantiating an OBUFE in an HDL design, FPGA Express
will also place an OBUF after the OBUFE and cause multiple drivers errors during
the Translate phase of implementation (NGDBUILD).

ソリューション

1

Infer the functionality of the OBUFE. For example:

VHDL:
DOUT <= DATA when ENABLE='1' else 'Z';

Verilog:
assign DOUT = ENABLE ? DATA : 1'bZ;

2

Instantiate an OBUFT and invert the signal that is used for the T pin.
AR# 5682
作成日 02/16/1999
最終更新日 08/27/2001
ステータス アーカイブ
タイプ 一般