AR# 5697


SYNPLIFY: Using FDCE or FDPE support for 9500 synthesis


Keywords: Synplify, VHDL, Verilog, FDCE, FDPE, 9500

Urgency: Standard

General Description:

Is there support for FDCE or FDPE for logic that describes a flip-flop
with a CE?


Synplify uses FDC/FDP with some muxing logic to the input of D pin to
describe a flip-flop with a CE.

Xilinx intentionally withheld FDCE and FDPE flops from all the synthesis
vendors CPLD libraries so that they would not infer them into any designs
that would be run on the Alliance 1.5 fitter. Inferencing support for
FDCE/FDPE flops for 9500 XL is not scheduled to start until the 2.1i release.

Please see (Xilinx Solution 2977) on how to avoid inferring flip-flops with
CE pins using the syn_useenables attribute.

The 1.5 fitter has very simplistic support for CEs; there is no optimization
available in the event a CE input uses the macrocell in an inefficient way.
Also, the synthesis tools do not have information about the CPLD architecture
that would allow them to perform that optimization themselves. Therefore, any
CE inferencing in designs run through the 1.5i fitter would be expected to
generally produce inefficient results.

A fitter enhancement in 2.1i will perform the necessary CE optimization which
will allow synthesis tools to begin inferring CEs. When Xilinx releases the
Alliance toolkit for 2.1i, Xilinx will request all synthesis vendors to add
FDCE/FDPE to their CPLD libraries and begin inferring them into designs that
will run on Xilinx 2.1i or later.

The 1.5 fitter does support explicit instantiation of FDCE/FDPE flops. These
will unconditionally utilize the CE p-term of the 9500 XL macrocell.
AR# 5697
日付 09/10/2002
ステータス アーカイブ
種類 一般
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