AR# 5835


1.5i SP2 Virtex Map - Cannot satisfy LOC/RLOC constraint for CC8CE and FDRSE design


Keywords: map, rloc, counter, CC8CE, flip flop, FDRSE, satisfy

Urgency: Standard

General Description: When creating a schematic with an CC8CE
(8-bit counter using carry chain with clear and enable) the
design runs fine. However, when changing the FFS in the
counter to FDRSE, MAP errors out.

FATAL_ERROR:xvkma:xvkmapper.c:1691.1.112 - Cannot satisfy
LOC/RLOC constraint on comp $I1/$1I285 Process will terminate.
Please call Xilinx support.


A fix for this problem is included in 1.5i Service Pack 2. For more information see:

(Xilinx Solution #5887)
AR# 5835
日付 04/10/2000
ステータス アーカイブ
種類 一般
People Also Viewed