This answer record contains the Release Notes and Known Issues for the DDR4, DDR3, QDRII+, QDRIV, RLDRAM3, LPDDR3 UltraScale and UltraScale+ Cores and includes the following:
This Release Notes and Known Issues Answer Record is for the programmable logic memory interface IP cores supported in UltraScale and UltraScale+ based devices.
Memory IP Page:
https://www.xilinx.com/products/technology/memory.html#externalMemoryXilinx Forums:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
| DDR4 Version | DDR3 Version | RLDRAM3 Version | QDRII+ Version | QDRIV Version | LPDDR3 Version | Vivado Tools Version |
| v2.2 (Rev. 7) | v1.4 (Rev. 7) | v1.4 (Rev. 7) | v1.4 (Rev. 7) | v2.0 (Rev. 7) | v1.0 (Rev. 7) | 2019.1 |
| v2.2 (Rev. 6) | v1.4 (Rev. 6) | v1.4 (Rev. 6) | v1.4 (Rev. 6) | v2.0 (Rev. 6) | v1.0 (Rev. 6) | 2018.3 |
| v2.2 (Rev. 5) | v1.4 (Rev. 5) | v1.4 (Rev. 5) | v1.4 (Rev. 5) | v2.0 (Rev. 5) | v1.0 (Rev. 5) | 2018.2 |
| v2.2 (Rev. 4) | v1.4 (Rev. 4) | v1.4 (Rev. 4) | v1.4 (Rev. 4) | v2.0 (Rev. 4) | v1.0 (Rev. 4) | 2018.1 |
| v2.2 (Rev. 3) | v1.4 (Rev. 3) | v1.4 (Rev. 3) | v1.4 (Rev. 3) | v2.0 (Rev. 3) | v1.0 (Rev. 3) | 2017.4 |
| v2.2 (Rev. 2) | v1.4 (Rev. 2) | v1.4 (Rev. 2) | v1.4 (Rev. 2) | v2.0 (Rev. 2) | v1.0 (Rev. 2) | 2017.3 |
| v2.2 (Rev. 1) | v1.4 (Rev. 1) | v1.4 (Rev. 1) | v1.4 (Rev. 1) | v2.0 (Rev. 1) | v1.0 (Rev. 1) | 2017.2 |
| v2.2 | v1.4 | v1.4 | v1.4 | v2.0 | v1.0 | 2017.1 |
| v2.1 (Rev. 1) | v1.3 (Rev. 1) | v1.3 (Rev. 1) | v1.3 (Rev. 1) | v1.2 (Rev. 1) | 2016.4 | |
| v2.1 | v1.3 | v1.3 | v1.3 | v1.2 | 2016.3 | |
| v2.0 (Rev. 1) | v1.2 (Rev. 1) | v1.2 (Rev. 1) | v1.2 (Rev. 1) | v1.1 (Rev. 1) | 2016.2 | |
| v2.0 | v1.2 | v1.2 | v1.2 | v1.1 | 2016.1 | |
| v1.1 | v1.1 | v1.1 | v1.1 | v1.0 | 2015.4 | |
| v1.0 | v1.0 | v1.0 | v1.0 | 2015.3 | ||
| v7.1 | v7.1 | v7.1 | v7.1 | 2015.2 | ||
| v7.0 | v7.0 | v7.0 | v7.0 | 2015.1 | ||
| v6.1 | v6.1 | v6.1 | v6.1 | 2014.4 | ||
| v6.0 | v6.0 | v6.0 | v6.0 | 2014.3 | ||
| v5.0 (Rev. 1) | v5.0 (Rev. 1) | v5.0 (Rev. 1) | v5.0 (Rev. 1) | 2014.2 | ||
| v5.0 | v5.0 | v5.0 | v5.0 | 2014.1 |
Starting with the release of Vivado 2015.3 the MIG wizard is no longer used.
A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.
For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:
https://www.xilinx.com/products/technology/memory.html#externalMemory
For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).
Table 2 provides answer records for general guidance when using UltraScale family external memory interface IP.
Table 2: General Guidance
| Answer Record | Title |
|---|---|
| (Xilinx Answer 59625) | MIG UltraScale - Design Methodology Checklist |
| (Xilinx Answer 61304) | MIG UltraScale - Clocking Guidelines and Requirements |
| (Xilinx Answer 68937) | MIG UltraScale DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide |
| (Xilinx Answer 71119) | UltraScale/UltraScale+ Memory IP - Reading and Understanding the Calibration Margins Reported in the MIG Dashboard |
| (Xilinx Answer 63462) | MIG UltraScale - Sample CSV data file for creating Custom Parts |
| (Xilinx Answer 63831) | MIG UltraScale - Migrating and Upgrading IP into 2015.1 |
| (Xilinx Answer 61598) | Design Advisory Master Answer Record for Kintex UltraScale FPGA |
| (Xilinx Answer 61930) | Design Advisory Master Answer Record for Virtex UltraScale FPGA |
| (Xilinx Answer 62483) | Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements |
| (Xilinx Answer 68169) | Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs |
Known and Resolved Issues
Table 3 provides a list of the individual release notes and known issue answer records for each UltraScale family external memory interface IP.
Table 3: UltraScale Family External Memory IP Release Notes and Known Issues Answer Records
| Answer Record | Title |
|---|---|
| (Xilinx Answer 69035) | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues |
| (Xilinx Answer 69036) | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues |
| (Xilinx Answer 69037) | UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues |
| (Xilinx Answer 69038) | UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues |
| (Xilinx Answer 69039) | UltraScale/UltraScale+ QDRIV - Release Notes and Known Issues |
| (Xilinx Answer 69040) | UltraScale/UltraScale+ LPDDR3 - Release Notes and Known Issues |
Table 4 provides a list of known and resolved issues that apply to all UltraScale family external memory interface IP.
Table 4: Known and Resolved Issues
| Answer Record | Title | Version Found | Version Fixed |
|---|---|---|---|
| (Xilinx Answer 72044) | UltraScale/UltraScale+ Memory IP - Default Vivado Simulation Behavior Change in 2018.2 and Later Versions | 2018.2 | NF |
| (Xilinx Answer 69947) | UltraScale Memory IP - designs giving hold violations | 2017.1 | Not Resolved |
| (Xilinx Answer 69827) | UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces | 2017.2 | 2017.3 |
| (Xilinx Answer 69611) | UltraScale/UltraScale+ Memory IP - Example Design - Advanced Traffic Generator (ATG) usage related data compare errors | 2014.1 | NAB |
| (Xilinx Answer 69324) | UltraScale+ MPSoC Memory IP - The SFVC784 package has incorrect data rates in PL Memory Interfaces | 2017.1 | 2017.2 |
| (Xilinx Answer 69291) | UltraScale+ MPSoC Memory IP - The SFVA625 package does not support PL Memory Interfaces | 2017.1 | 2017.2 |
| (Xilinx Answer 68976) | UltraScale/UltraScale+ Memory IP - User addition of pblock might cause skew violations between RIU_CLK and PLL_CLK pins of BITSLICE_CONTROL | 2015.3 | Not Resolved |
| (Xilinx Answer 67392) | UltraScale/UltraScale+ Memory IP - pulse width violations can occur | 2016.2 | 2017.1 |
| (Xilinx Answer 67967) | UltraScale/UltraScale+ Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range | 2016.3 | 2016.4 |
| (Xilinx Answer 67957) | UltraScale/UltraScale+ Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP | 2016.3 | 2016.4 |
| (Xilinx Answer 67933) | UltraScale/UltraScale+ Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part | 2016.3 | 2017.1 |
| (Xilinx Answer 68028) | UltraScale/UltraScale+ Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps) | 2016.3 | 2017.1 |
| (Xilinx Answer 67684) | UltraScale/UltraScale+ Memory IP - moving IP that uses custom memory parts (CSV) might cause problems | 2016.2 | 2016.3 |
| (Xilinx Answer 67335) | UltraScale/UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skipped | 2016.2 | 2016.3 |
| (Xilinx Answer 66951) | UltraScale/UltraScale+ Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check | 2016.1 | 2016.3 |
| (Xilinx Answer 66360) | UltraScale/UltraScale+ Memory IP - Core Container does not include *.csv file when a custom memory part is created | 2015.3 | 2016.3 |
| (Xilinx Answer 67225) | UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IP | 2016.1 | 2016.3 |
| (Xilinx Answer 67224) | UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCM | 2016.1 | 2016.2 |
| (Xilinx Answer 67164) | UltraScale+ Memory IP - timing failures occur due to high congestion levels | 2016.2 | NF |
| (Xilinx Answer 66800) | UltraScale Memory IP - When the reset_n pin is located in a bank with an I/O Standard that has an incompatible voltage level the following error is seen during 'opt_design': [Mig 66-99] | 2016.1 | NF |
| (Xilinx Answer 59990) | UltraScale/UltraScale+ Memory IP - IPI MIG simulation does not have memory models available | 2016.3 | NF |
| (Xilinx Answer 66678) | UltraScale/UltraScale+ Memory IP - Design fails during 'opt_design' when using Custom CSV | 2015.2 | 2016.1 |
| (Xilinx Answer 65431) | UltraScale/UltraScale+ Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraint | 2015.3 | 2016.1 |
| (Xilinx Answer 62543) | UltraScale/UltraScale+ Memory IP - Certain speed grades incorrectly prevent previously allowed input clock periods | 2014.3 | 2016.1 |
| (Xilinx Answer 65370) | UltraScale/UltraScale+ Memory IP - pblocks containing Memory IP logic must be contained within the same clock region the memory I/O is located in | 2015.3 | 2015.4 |
| (Xilinx Answer 65327) | UltraScale/UltraScale+ Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it. | 2015.3 | 2015.4 |
| (Xilinx Answer 64778) | UltraScale/UltraScale+ Memory IP - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bank | 2015.1 | 2015.4 |
| (Xilinx Answer 64188) | UltraScale/UltraScale+ Memory IP - sys_rst missing set_false_path constraint | 2015.1 | 2015.4 |
| (Xilinx Answer 64071) | UltraScale/UltraScale+ Memory IP - Custom Memory Parts Fail Simulation | 2015.1 | 2015.3 |
| (Xilinx Answer 64923) | UltraScale/UltraScale+ Memory IP - Hardware Manager Xicom error messages occurring after programming device | 2015.1 | 2016.3 |
| (Xilinx Answer 64069) | UltraScale/UltraScale+ Memory IP - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pins | 2015.1 | 2015.2 |
| (Xilinx Answer 64431) | UltraScale/UltraScale+ Memory IP - [Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0 | 2014.4 | 2015.1 |
| (Xilinx Answer 62774) | UltraScale/UltraScale+ Memory IP - timing failures may be seen with MIG generated example design | 2014.4 | 2015.1 |
| (Xilinx Answer 64070) | UltraScale/UltraScale+ Memory IP - Designs with multiple controllers might generate ERROR::34 message | 2014.4 | 2015.1 |
| (Xilinx Answer 62649) | UltraScale/UltraScale+ Memory IP - GUI allows core generation even if all address and control byte lanes have not been selected | 2014.3 | 2015.1 |
| (Xilinx Answer 59989) | UltraScale/UltraScale+ Memory IP - Critical warnings are generated when multiple MIG instances are included in a design | 2014.1 | 2015.1 |
| (Xilinx Answer 59991) | UltraScale/UltraScale+ Memory IP - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful | 2014.1 | 2015.1 |
| (Xilinx Answer 61696) | UltraScale/UltraScale+ Memory IP - The funcsim.v/.vhdl structural simulation model is not supported | 2014.2 | NF |
| (Xilinx Answer 61076) | UltraScale/UltraScale+ Memory IP - Multiple instances of MIG IP fails with "[Place 30-678] Failed to do clock region partitioning" | 2014.2 | 2014.3 |
| (Xilinx Answer 60953) | UltraScale/UltraScale+ Memory IP - Output Products must be generated before opening the IP Example Design | 2014.2 | 2014.3 |
| (Xilinx Answer 64410) | UltraScale/UltraScale+ Memory IP - Can either external or internal VREF be used? | 2014.1 | NAB |
| 04/16/2014 | Initial release |
| 06/04/2014 | Updated for 2014.2 |
| 10/01/2014 | Updated for 2014.3 |
| 10/16/2014 | Added link to Hardware Debug Guide |
| 11/07/2014 | Updated for 2014.4 |
| 12/16/2014 | Added AR62930 |
| 01/08/2015 | Added AR63261 |
| 04/15/2015 | Updated for 2015.1 release |
| 06/24/2015 | Updated for 2015.2 release |
| 07/06/2015 | Added AR64887 |
| 07/09/2015 | Added 64923 |
| 08/07/2015 | Added 64946 |
| 09/30/2015 | Updated for 2015.3 |
| 11/24/2015 | Updated for 2015.4 |
| 01/26/2015 | Added 66471 |
| 04/13/2016 | Updated for 2016.1 release |
| 09/19/2016 | Added 67891 |
| 10/05/2016 | Updated for 2016.3 release |
| 02/08/2017 | Added 61598, 61930, 62483, 64856, 68169 |
| 03/24/2017 | Updated for 2017.1 release, Added LPDDR3, Added 66471, 67979, 67956, 68894, 68895, 68843 |
| 04/18/2017 | Created Answer Records for Each Memory Controller Type |
| 06/05/2017 | Updated for 2017.2 |
| 07/31/2017 | Updated debugging link to AR#68937 |
| 12/13/2017 | Updated formatting and updated for 2017.4 |
| 03/14/2018 | Updated for 2018.1 and added 71119 |
| 09/20/2018 | Updated for 2018.3 |
| 05/02/2019 | Updated for 2019.1 |
| 08/23/2019 | Added AR 72044 |
| タイトル | サイズ | ファイルタイプ |
|---|---|---|
| memory_device_support_ddr4.xlsx | 17 KB | XLSX |
| memory_device_support_ddr3.xlsx | 18 KB | XLSX |
| memory_device_support_lpddr3.xlsx | 16 KB | XLSX |
| memory_device_support_qdriiplus.xlsx | 16 KB | XLSX |
| memory_device_support_qdriv.xlsx | 16 KB | XLSX |
| memory_device_support_rldram3.xlsx | 17 KB | XLSX |
| Answer Number | アンサータイトル | 問題の発生したバージョン | 修正バージョン |
|---|---|---|---|
| 62603 | Virtex UltraScale FPGA VCU108 評価キット - 既知の問題およびリリース ノートのマスター アンサー | N/A | N/A |