General Description: The design inputs two or more clock signals using the dedicated clock iobs. The clocks are connected to the CLKIN pin on the CLKDLL. The outputs of the CLKDLL are then used to drive the synchronous elements in the design. Both CLKDLLs reset pin is driven by the same signal.
When TRCE/Timing Analyzer evaluates the inter-clock relationships there is the possibility of large skew being reported. This is the result of the reset net coming from one source to multiply DLLs. To verify this open the design in EPIC and check the delay on both CLKDLLs reset input. The difference between the two reported delays is reported as skew.
Add the following constraint to the PCF file: