Problem description: CLKDV_DIVIDE attribute has to be entered in the ucf file. How can one simulate this behavior in pre-synthesis functional simulation?
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NOTE: The HDL codes given below may not be synthesizable. Users need to modify the code properly in order to finish the synthesis.
For VHDL designs, there are 2 ways to simulate this behavior.
1. Use generic statement in the vhdl code. Here is an example code:
library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all;
entity useclk is port (Din, clk : in std_logic; Dout, locked : out std_logic); end useclk;
architecture useclk_arch of useclk is
component BUFG port (I: in std_logic; O: out std_logic); end component;
component CLKDLL generic (CLKDV_DIVIDE : real); port ( CLKIN, CLKFB, RST : in std_logic; CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic); end component;
signal clk_int, clk_bufg, clk_div2,clk_div2_bufg, lock1st,reset2nd,a,b,c,d,e,gd: std_logic;
begin
gd<='0';
U0 : BUFG port map (I=>clk_int, O=>clk_bufg);
U1 : CLKDLL generic map( CLKDV_DIVIDE=>2.0)
port map( CLKIN=>clk, RST=>gd, CLKFB=>clk_bufg, CLK0=>clk_int, CLK90=>b, CLK180=>c, CLK270=>d, CLKDV=>clk_div2, CLK2X=>a, LOCKED=>lock1st); U2 : BUFG port map (I=>clk_div2, O=>clk_div2_bufg); process (clk_div2_bufg) begin if (clk_div2_bufg'event and clk_div2_bufg='1') then Dout<=Din; end if; end process;
end useclk_arch;
2. Use configuration statements in the testbench.
Here is one example:
library IEEE; use IEEE.std_logic_1164.all;
library UNISIM; use UNISIM.vcomponents.all;
configuration cfg_clkdlls_tb of clkdlls_tb is for tb for uut_clkdlls : clkdlls use entity work.clkdlls(struct); for struct for all : clkdll use entity unisim.clkdll(clkdll_v) generic map (DUTY_CYCLE_CORRECTION => FALSE, CLKDV_DIVIDE => 1.5); end for; end for; end for; end for; end cfg_clkdlls_tb;
in which:
cfg_clkdlls_tb: Name of the the configuration clkdlls_tb: Entity of the testbench tb: Architecture name of the testbench uut_clkdlls: Instance name of the top level design in the testbench clkdlls: Component name of the top level design struct: Architecture name of the top level RTL vhdl code.