We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6068

2.1i, V1.5 COREGEN, DATASHEETS: the CLB count is incorrect for a 16-bit wide loadable registered adder


Keywords: coregen, loadable, registered, adder, clb

Urgency: Standard

General Description:
The datasheet for the CORE Generator Registered Adder states that the
16-bit wide non-loadable function requires 10 CLB's, while the Registered
Loadable Adder datasheet indicates that a loadable version of the adder
with the same bit width requires only 9 CLBs.


The Registered Loadable Adder datasheet is in error--both versions of a 16-bit
adder require 10 CLB's.
AR# 6068
作成日 03/31/1999
最終更新日 08/29/2001
ステータス アーカイブ
タイプ 一般