UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6184

1.5i: 9500XL: Hitop : BUFT and Clock polarity inverted

説明

Keywords: 9500XL, polarity, inversion

Urgency: Hot

General Description: A problem was detected on a few select cases
with designs showing inverted output from a clock signal or obuft.

ソリューション

Please refer to solution 6427 for the ftp site location of the patch to be
installed on top of 1.5i with Service Pack 2. (http://www.xilinx.com/techdocs/6427.htm)

For a temporary workaround you can place a keep attribute on the tristate
signal to prevent the polarity inversion.
AR# 6184
作成日 04/13/1999
最終更新日 08/27/2001
ステータス アーカイブ
タイプ 一般