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General Description: The .vhd and .v files produced by CORE Generator are only for functional simulation. They are NOT intended to be used for synthesis. Attempting to synthesize these models will give you suboptimal results. In most cases, simulation-specific constructs used in these models will prevent you from synthesizing them altogether.
Implementation of the CORE Generator module is completely specified by the .EDN EDIF netlist generated for it. For HDL design flows, this should be instantiated in your design as a "black box."
Do not attempt to synthesize the .v and .vhd files generated by CORE Generator.