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AR# 6260

V1.5, V1.4 CORE Generator, VERILOG, VHDL - VHD and .v files produced by COREGEN are only for simulation.

説明

Keywords: VHD, .vhd, .v, Verilog, CORE Generator, COREGen, simulate

Urgency: Standard

General Description:
The .vhd and .v files produced by CORE Generator are only for functional simulation. They are NOT intended to be
used for synthesis. Attempting to synthesize these models will give you suboptimal results. In most
cases, simulation-specific constructs used in these models will prevent you from synthesizing them
altogether.

Implementation of the CORE Generator module is completely specified by the .EDN EDIF netlist
generated for it. For HDL design flows, this should be instantiated in your design as a "black box."

ソリューション

Do not attempt to synthesize the .v and .vhd files generated by CORE Generator.
AR# 6260
作成日 08/31/2007
最終更新日 02/15/2001
ステータス アーカイブ
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