The JESD204 Link Error Status (Lanes 0 to 7) register should clear all status bits automatically upon reading the register.
For JESD204 v5.2 and v6.0, register behavior is not as expected.
A read cannot clear the register when multiple lanes are implemented.
This has been resolved in JESD204 v6.1, as outlined in (Xilinx Answer 64619) - 2015.1 Vivado IP Release Notes - All IP Change Log Information:
"Fixed issue with Rx Link Error Status Registers (0x01C and 0x03C) not auto clearing after a read for multi-lane designs"
Customers are asked to migrate to Vivado 2015.1 with JESD204 v6.1 if they experience this issue.
If migration to Vivado 2015.1 is not an option, a patch is available for Vivado 2014.4 upon application to Xilinx Technical Support.
To apply, create a Service Request referencing this Answer Record number.
The preferred resolution is to migrate to Vivado 2015.1.