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AR# 63441

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v14.3 (Rev. 1) - UltraScale GTH - free running clock update


The core has an independent clock input set at 300Mhz due to IDELAY logic used in the example design GMII external interface.  

This clock can now go down to 200Mhz if IDELAY logic is used.

The independent clock is also used to create the GTwizard freerun and DRP clocks. 

The DRP clock is generated with a divide by 6 BUFR to run at 50Mhz. 

If a 200Mhz clock source is available instead, it can be changed to be a divide by 4 to keep this clock at 50Mhz.


In the v14.3 (Rev. 1) core in 2014.4, both the GTwizard freerun and DRP clocks should be running at 50Mhz.  

Currently freerun is driven by a 300Mhz independent clock input and DRP is driven by independent_clock_bufgdiv6.    


If IDELAY logic is not used, a 50Mhz clock input can also be used instead of dividing down a 200-300Mhz clock. 

At the core level, independent_clock and independent_clock_bufgdiv6 should be driven by the 50mhz clock as these are feeding the DRP and freerun clock to the GT wizard.

This will be fixed in the core in the 2015.1 release.



To drive both the free running and independent clock at 50Mhz, do the following:

In the core_name_shared_logic.v/vhd drive both the independent_clock_bufg and  independent_clock_bufgdiv6 inputs to the core with the divided down independent_clock_bufgdiv6 signal:

Change from:

      .independent_clock_bufg        (independent_clock_bufg),
      .independent_clock_bufgdiv6           (independent_clock_bufgdiv6),


      .independent_clock_bufg        (independent_clock_bufgdiv6),
      .independent_clock_bufgdiv6           (independent_clock_bufgdiv6),

AR# 63441
日付 01/28/2015
ステータス アクティブ
種類 一般
  • Ethernet 1000BASE-X PCS/PMA or SGMII