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AR# 6359

10.1 Floorplanner/Virtex - "ERROR:xvkpu:19 - The symbol clock_in.PAD failed to join a global clock I/O component..."


After I place the CLKIOB and BUFG components, the following error occurs in MAP: 


"ERROR:xvkpu:19 - The symbol clock_in.PAD failed to join a global clock I/O component as required. The symbol has a constraint (LOC=P101) that specifies an illegal physical site for the component. Please correct the constraint value."  


Why does this error occur?


To work around this issue: 

- Place the CLKIOB in an IOB that contains a BUFG 

- Consult the Data Book for the correct location to place it 

- Do not place it at all, and let the tools place it 


This will be fixed in the next major software release.


If you are trying to use the GCLKIOB as user I/O (i.e., you do not want the signal from the GCLKIOB to use the BUFG), you must make the following connection: 


GCLKIOB (IPAD) -> IBUFG -> User Logic 


If you are using schematic entry, insert the IBUFG in place of the IBUF. If you are using VHDL/Verilog, instantiate an IBUFG.

AR# 6359
日付 05/14/2014
ステータス アーカイブ
タイプ 一般