The Kintex UltraScale FPGA KCU105 Evaluation Kit Checklist is useful to debug board-related issues and to determine if applying for a Board RMA is the next step.
Before working through the KCU105 Board Debug Checklist, please review (Xilinx Answer 63175) - Kintex UltraScale KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record, as the issue you are faced with might be covered there.
1. Switch / Jumper Settings
2.Board Power
3.Cable detection
4.JTAG Initialization
The following debug steps assume steps 1-4 have been checked and are working:
5.JTAG Configuration
6.Master SPI Configuration
7.PCIe
8.IBERT
9.DDR4
10.Interface Tests
11.Known Issues for KCU105
1. Switch / Jumper Settings
Default Switch and Jumper Settings for the KCU105 are:
Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.
a. DIP Switch Default Settings:
b. DIP Switch SW15 Mode Settings:
Mode settings switches M2:0] are wired to SW15 pins 4-6. The default settings for SW15 (Mode Settings) is listed below.
c. Default Jumper Settings:
Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the KCU105 Evaluation Kit.
The status of the Power-ON LEDs is an indication of board health.
a. Check the status of the following LEDs at Power-ON:
b. Ethernet PHY status LEDs
These LEDs are visible on the left edge of the KCU105 board when it is installed into a PCIe slot in a PC chassis.
The two PHY status LEDs are integrated into the metal frame of the P3 RJ-45 connector, as shown below:
The KCU105 uses a USB A-to-micro-B cable plugged into the KCU105 Digilent USB-to-JTAG module, U115.
A 2-mm JTAG header (J3) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II.
a. USB A-to-micro-B cable:
4. JTAG Initialization
The status of the board JTAG chain is checked using Xilinx Tools (Hardware Manager in Vivado).
To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:
1. Remove any FMC cards from KCU105.
2. Set the mode switch SW15 for JTAG mode (101).
3. Power up KCU105 on the bench (not in a PC chassis).
4. Connect the Digilent USB A-to-micro B cable to the KCU105 (through the Digilent onboard USB-to-JTAG configuration logic module - U115 - through header J87).
5. Check that the Digilent device shows up in the Device Manager.
6. Ensure Xilinx tools (Vivado 2014.4.1 or later - preferably the latest version of tools that support the KCU105) are correctly installed.
7. Launch Vivado Hardware Manager - is the cable identified correctly?
If following the above steps does not allow you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.
Connect the Platform Cable USB to header J3, and connect to your PC.
Ensure Xilinx tools (preferably the latest version of tools that support the KCU105) are correctly installed.
Launch Vivado Hardware Manager - is the cable identified correctly?
If following the above steps does not allow you to initialize the JTAG chain, please review the Support Webpage for your available Support options.
http://www.xilinx.com/support/clearexpress/websupport.htm
5. JTAG Configuration
If the JTAG chain initializes okay but JTAG configuration fails, check the following:
a) Verify the mode switch settings for JTAG configuration mode:
SW15-2 (M2) 1
SW15-3 (M1) 0
SW15-4 (M0) 1
b) In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.
c) Pulse the PROG push button on the KCU105 (SW4).
Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.
d) Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.
The Configuration Solution Center is available to address all questions related to Configuration.
If the above steps fail to enable JTAG configuration, please review the Support Webpage for your available Support options.
6.Master SPI configuration
The Vivado Hardware Manager can be used to indirectly program the dual-QSPI flash devices (U35, U36) on the KCU105.
With both SW15.6 (FPGA_M2) and SW15.5 (SYSCTLR_ENABLE) in the OFF (disable the SYSCTLR_ENABLE) position, a bitstream programmed into the dual-QSPI flash devices (U35, U36) is used to configure the UltraScale FPGA U1.
If you have loaded a ".mcs" file into the SPI flash on the KCU105, and subsequent Master SPI configuration of the Kintex UltraScale device fails, the following points should be checked:
a. If the ".mcs" file is correctly loaded, you will see the selected FLASH device added to the JTAG chain, as shown here:
By clicking on the flash device, you will see the MCS file succesfully loaded:
If you do not see the FLASH device attached to the XCKU040 device as shown, see the Vivado Design Suite User Guide: (UG908) Programming and Debugging.
b. Verify the mode switch settings for Master SPI configuration:
S15-6 (M2) 0
S15-5 (M1) 0
S15-4 (M0) 1
c. In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.
d. Pulse the PROG push button on the KCU105 (SW4), to attempt to reload the FPGA with the configuration image.
e. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.
The Configuration Solution Center is available to address all questions related to Configuration.
If the above steps fail to enable SPI configuration, please review the Support Webpage for your available Support options.
7. PCIe
If the KCU105 configures correctly, but the PCIe interface does not operate as expected, check the following:
a) Do NOT plug a PC ATX power supply 6-pin connector into J15 on the KCU105 board.
The ATX 6-pin connector has a different pinout than J15.
Connecting an ATX 6-pin connector into J15 will damage the KCU105 board and void the board warranty.
To install and power the board correctly, follow the instructions given in (UG917) KCU105 Evaluation Board User Guide - Appendix E - Board Setup.
http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf
b) Check J74, lane width, is set correctly for your application.
c) See one of the following Answer Records, covering Known Issues for PCI Express, including Kintex UltraScale:
(Xilinx Answer 57945) - UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.3 and newer tools versions.
d) Download and run the KCU105 PCIe Example Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 PCIe Example Design.
Follow the associated PDF.
All are available from the KCU105 Example Designs page.
http://www.xilinx.com/products/boards-and-kits/kcu105.html
e) Read the KCU105 PCIe Example Design document: KCU105 PDF: xtp350.pdf and follow the instructions within.
h) Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.
The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.
If the above steps fail to resolve the PCIe issue, please review the Support Webpage for your available Support options.
8. IBERT
NOTE: Running IBERT requires the installation of Vivado ILA.
A device-locked license for this software is provided with the Kintex UltraScale KCU105 Evaluation Kit.
If the KCU105 configures correctly, but IBERT does not operate as expected, check the following:
a) If using MGT loopback, ensure that you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:
More information can be found in the KCU105 GTH IBERT PDF, from the KCU105 Example Designs page.
http://www.xilinx.com/products/boards-and-kits/kcu105.html
b) Download and run the KCU105 GTH IBERT Example Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 GTH IBERT Example Design.
Follow the associated PDF.
All are available from the KCU105 Example Designs page.
http://www.xilinx.com/products/boards-and-kits/kcu105.html
.
c) Read the KCU105 GTH IBERT Example Design document: KCU105 GTH IBERT PDF: xtp346.pdf and follow the instructions therein.
d) IBERT Design Assistant: (Xilinx Answer 45562).
If the above steps fail to resolve the IBERT issue, please review the Support Webpage for your available Support options.
9.DDR4
If a problem is suspected with DDR4 / MIG, check the following:
a) Ensure that the DDR4 DIMM component memory is inserted correctly.
b) Download and run the KCU105 MIG Example Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 MIG Example Design.
Follow the associated PDF.
All are available from the KCU105 Example Designs page.
http://www.xilinx.com/products/boards-and-kits/kcu105.html
d) Review (Xilinx Answer 34243) - Xilinx MIG Solution Center.
The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.
If the above steps fail to resolve the DDR4 issue, please review the Support Webpage for your available Support options.
10. Interface Tests
(Xilinx Answer 63799) - Kintex UltraScale FPGA KCU105 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the KCU105 are working correctly.
This Answer Record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
If the above tests fail to resolve the issue, please review the Support Webpage for your available Support options.
11. Known Issues for KCU105
All Known Issues for the Kintex UltraScale FPGA KCU105 Evaluation Kit are listed in (Xilinx Answer 63175) - Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record.
If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please review the Support Webpage for your available Support options.
AR# 63739 | |
---|---|
日付 | 11/19/2015 |
ステータス | アクティブ |
種類 | 一般 |
Boards & Kits |