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AR# 64661

LogiCORE IP Video On Screen Display (OSD) v5.01a - Why does the AXI Stream reset ARESETn seems to hold all control registers in reset?

説明

Why does the AXI Stream reset ARESETn seems to hold all control registers in reset?

While debugging the OSD setup the AXI-Lite interface to the core was basically non-functional.

Direct reads to the core memory space always return 0 even if the users has just written to the said registers.

What can be the reason for this?

ソリューション

The Product Guide (PG010) v5.01 on Page 22 states that the AXI4-Lite interface is not affected by the ARESETn:


"The ARESETn pin is an active-low, synchronous reset input pertaining to only AXI4-Stream interfaces. ARESETn supersedes ACLKEN, and when set to 0, the core resets at the next rising edge of ACLK even if ACLKEN is de-asserted.
The ARESETn signal must be synchronous to the ACLK and must be held low for a minimum of 32 clock cycles of the slowest clock.
The AXI4-Lite interface is unaffected by the ARESETn signal"


This is a known issue where the ARESETn holds the control registers in reset, and must be deasserted in order to read and write to the AXI4-Lite interface.

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マスター アンサー レコード

AR# 64661
日付 06/30/2015
ステータス アクティブ
種類 一般
デバイス
  • Virtex-6
ツール
  • ISE Design Suite - 14.7
IP
  • On-Screen Display
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