This answer record contains the Release Notes and Known Issues for the DMA Subsystem for PCI Express Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2015.3 and newer tool versions.
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Supported devices can be found in the following three locations:
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.1 (Rev4) | 2019.2 |
| v4.1 (Rev3) | 2019.1 |
| v4.1 (Rev2) | 2018.3 |
| v4.1 (Rev1) | 2018.2 |
| v4.1 | 2018.1 |
| v4.0 (Rev1) | 2017.4 |
| v4.0 | 2017.3 |
| v3.1(Rev1) | 2017.2 |
| v3.1 | 2017.1 |
| v3.0 (Rev1) | 2016.4 |
| v3.0 | 2016.3 |
| v2.0 (Rev1) | 2016.2 |
| v2.0 | 2016.1 |
| v1.0 (Rev1) | 2015.4 |
v1.0 | 2015.3 |
Tactical Patch
The following table provides a list of tactical patches for the DMA Subsystem for PCI Express core applicable on corresponding Vivado tool versions.
| Answer Record | Core Version (After installing the Patch) | Tool Version |
|---|---|---|
| (Xilinx Answer 66500) | v1.0 (Rev. 66500) | 2015.4 |
| (Xilinx Answer 67111) | v2.0 (Rev. 67111) | 2016.1 |
| (Xilinx Answer 67421) | v2.0 (Rev. 67421) | 2016.2 |
| (Xilinx Answer 68111) | v3.0 (Rev. 68111) | 2016.3 |
| (Xilinx Answer 68259) | v3.0 (Rev. 68259) | 2016.3 |
| (Xilinx Answer 68478) | v3.1 (Rev. 68478) | 2016.4 |
| (Xilinx Answer 68512) | v3.1 (Rev. 68512) | 2016.4 |
| (Xilinx Answer 69275) | v3.1 (Rev. 69275) | 2017.1 |
| (Xilinx Answer 69405) | v3.1(Rev. 69405) | 2017.2 |
| (Xilinx Answer 70012) | v4.0 (Rev. 70012) | 2017.3 |
| (Xilinx Answer 70324) | v4.0 (Rev 70324) / v4.0 (Rev 70325) | 2017.3/2017.4 |
| (Xilinx Answer 70877) | v4.0(Rev. 70877) | 2017.4 |
| (Xilinx Answer 71012) | v4.0 (Rev.71012) / v4.1 (Rev. 71012) | 2017.4/2018.1 |
| (Xilinx Answer 71052) | v4.1 (Rev. 71052) | 2018.1 |
| (Xilinx Answer 71147) | v4.1 (Rev. 71147) | 2018.1 |
| (Xilinx Answer 71169) | v4.1 (Rev. 71169) | 2018.1 |
| (Xilinx Answer 71375) | v4.1 (Rev. 71375) | 2018.2 |
| (Xilinx Answer 71634) | v4.1 (Rev. 71634) | 2018.2 |
| (Xilinx Answer 72010) | v4.1 (Rev. 72010) | 2018.3 |
| (Xilinx Answer 72034) | v4.1 (Rev. 72034) | 2018.3 |
| (Xilinx Answer 72439) | v4.1 (Rev. 72439) | 2019.1 |
| (Xilinx Answer 72747) | v4.1(Rev. 72747) | 2019.1 |
| (Xilinx Answer 73001) | v4.1 (Rev 73001) | 2019.2 |
Note:
Design Advisory
| (Xilinx Answer 70838) | Design Advisory for AXI SmartConnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption |
Known and Resolved Issues
The following table provides known issues for the DMA Subsystem for PCI Express core, starting with v1.0, initially released in Vivado 2015.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 73001) | ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'design_1_xdma_4_2_pcie4_ip'.. | v4.1 (Rev 4) | Not Resolved Yet; Tactical Path Provided |
| (Xilinx Answer 72747) | DMA Subsystem for PCI Express in "AXI-Bridge" mode - "NUM_READ_OUTSTANDING" and "NUM_WRITE_OUTSTANDING" parameters of M_AXI_B port reset to "2" after validate BD is executed in IP Integrator | v4.1 (Rev 3) | Not Resolved Yet; Tactical Path Provided |
| (Xilinx Answer 72439) | Gen4 Support in Virtex UltraScale+ HBM devices | v4.1 (Rev 3) | Not Resolved Yet; Tactical Path Provided |
| (Xilinx Answer 72034) | Tactical patch for issue fixes
| v4.1 (Rev. 2) | v4.1 (Rev 3) |
| (Xilinx Answer 72010) | Tactical patch for issue fixes
| v4.1 (Rev. 2) | v4.1 (Rev 3) |
| (Xilinx Answer 71634) | Tactical patch for issue fixes
| v4.1 | v4.1 (Rev2) |
| (Xilinx Answer 71375) | Tactical patch for issue fixes
| v4.1 | v4.1 (Rev2) |
| (Xilinx Answer 71169) | Core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters by 3 bits | v4.1 | v4.1 (Rev1) |
| (Xilinx Answer 71147) | Tactical patch for issue fixes
| v4.1 | v4.1 (Rev1) |
| (Xilinx Answer 71105) | MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode | v4.1 | Work-around Available |
| (Xilinx Answer 71052) | Bridge Mode performance issue in Gen3x8 256 bit Configuration | v4.1 | v4.1 (Rev1) |
| (Xilinx Answer 70877) | c2h_dsc_byp_ready may deassert permanently in Descriptor Bypass mode | v4.0 (Rev1) | v4.1 (Rev1) |
| (Xilinx Answer 71012) | PCIe to DMA Bypass BAR size cannot be set to 32GB when 64Bit enable is selected | v4.0(Rev1) / v4.1 | v4.1 (Rev1) |
| (Xilinx Answer 70324) | Tactical patch for issue fixes Issue 1: If Max Read Request Size = 128B, MPS= 128B and transfer length= 129B are set, DMA transfer does not complete. The following issues are seen:
Issue 2:
| v4.0 / v4.0 (Rev1) | v4.1 |
| (Xilinx Answer 70012) | Tactical patch for issue fixes and enhancements DMA / Bridge Subsystem for PCI Express v4.0 - (Vivado 2017.3) All of the issues listed are for both DMA Mode and Bridge Mode
| v4.0 | v4.0(Rev1) |
| (Xilinx Answer 69405) | Tactical patch for issue fixes and enhancements DMA / Bridge Subsystem for PCI Express v3.1 (Rev. 1) - (Vivado 2017.2) All of the issues listed are for both DMA Mode and Bridge Mode
| v3.1(Rev1) | v4.0 |
| (Xilinx Answer 69275) | Support for x8gen3 in -2LV UltraScale devices | v3.1 | v3.1(Rev1) |
| (Xilinx Answer 68512) | Tactical patch for issue fixes and enhancements
| v3.0 (Rev1) | v3.1 |
| (Xilinx Answer 68478) | x16 Support in xczu7ev (fbv900 and ffvc1156) Devices | v3.0 (Rev1) | v3.1 |
| (Xilinx Answer 68617) | x16 lane support in VCU118 (xcvu9p-flga2104 -2L device) | v3.0 (Rev 1) | v3.1 |
| (Xilinx Answer 68259) | FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. | v3.0 | v3.0(Rev1) |
| (Xilinx Answer 68205) | Gen3x8 on UltraScale -1, -1L, -1LV, -1H, -1HV devices and 250Mhz user clock support | v3.0 | v3.0(Rev1) |
| (Xilinx Answer 68111) | Tactical patch for issue fixes
| v3.0 | v3.0(Rev1) |
| (Xilinx Answer 67421) | Prefetchable support for 64-bit BAR | v2.0(Rev1) | V3.0 |
| (Xilinx Answer 66500) | IDLE STOP is not set correctly | v1.(Rev1) | v2.0 |
| (Xilinx Answer 67111) | Issue with Legacy Interrupt Mode and MSI-X Table Offset | v2.0 | v2.0(Rev1) |
Other Information:
| (Xilinx Answer 70706) | DMA/Bridge Subsystem for PCI Express (Vivado 2017.4) - Bridge Mode - Root Port - AXI transactions fail when no Endpoint is connected |
| (Xilinx Answer 71095) | DMA / Bridge Subsystem for PCI Express (Bridge Mode - Vivado 2017.4) - AXIBAR and AXIBAR_HIGHADDR are set incorrectly in an IP Integrator design resulting in DECERR during 64-bit S_AXI access |
| (Xilinx Answer 71105) | DMA Subsystem for PCI Express (Vivado 2018.1) - MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode |
| (Xilinx Answer 71427) | ERROR: [DRC REQP-1910] PCIE31_invalid_MCAPPERSTxB_driver |
| (Xilinx Answer 71322) | Reading AXI PCIe Gen3/XDMA Internal Registers using JTAG to AXI Master IP |
| (Xilinx Answer 71466) | ERROR: [Place 30-69] Instance xdma_app_i/led_2_obuf (OBUF drives I/O terminal xdma_app_i/leds[2]) is unplaced after IO placer |
| (Xilinx Answer 71730) | Clock Sharing with sys_clk requirements |
Revision History:
| Answer Number | アンサータイトル | 問題の発生したバージョン | 修正バージョン |
|---|---|---|---|
| 70012 | DMA/Bridge Subsystem for PCI Express および UltraScale+ PCI Express Integrated Block (Vivado 2017.3) - 問題の修正および機能の改善を含めた緊急パッチ | N/A | N/A |
| 70702 | Zynq UltraScale+ MPSoC - PS/PL PCIe ドライバー - リリース ノート | N/A | N/A |
| AR# 65443 | |
|---|---|
| 日付 | 11/27/2019 |
| ステータス | アクティブ |
| 種類 | リリース ノート |
| IP | |