I am running the Xilinx Design Manager (pld_dsgnmgr) on the edif file for my design that came from pld_men2edif. Upon selecting the Design -> options, and selecting Quicksim for my Simulation type, I let the tools implement. I do not get a time_sim.edn like I used to. When I edit the options for the Quicksim simulation I see that the simulation netlist name is set to time_sim How come it is not created?
Due to a change in the program pld_edif2tim, the Xilinx Design Manager will be writing out the backend EDIF netlist named design.edn (design being the input filename EDIF), instead of the filename time_sim.edn. The file design.edn will be created even though the option for the simulation netlist name is set to time_sim
The file must be named design.edn and you must run pld_edif2tim on this file name or it will error out. For example if the name of the file was time_sim.edn, the A2.1i pld_edif2tim prgram would error out that it could not find the directory time_sim_lib.