This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express Integrated Block Core and includes the following:
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
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Supported devices can be found in the following locations:
Version Table:
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v1.3 (Rev5) | 2019.1 |
| v1.3 (Rev4) | 2018.3 |
| v1.3 (Rev3) | 2018.2 |
| v1.3 (Rev2) | 2018.1 |
| v1.3 (Rev1) | 2017.4 |
| v1.3 | 2017.3 |
| v1.2 (Rev1) | 2017.2 |
| v1.2 | 2017.1 |
| v1.1 (Rev3) | 2016.4 |
| v1.1 (Rev2) | 2016.3 |
| v1.1 (Rev1) | 2016.2 |
| v1.1 | 2016.1 |
| v1.0 (Rev1) | 2015.4 |
| v1.0 | 2015.3 |
Tactical Patch
The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.
| Answer Record | Core Version (After installing the Patch) | Tool Version |
|---|---|---|
| (Xilinx Answer 72060) | v1.3 (Rev 72060) | 2018.3 |
| (Xilinx Answer 72034) | v1.3 (Rev. 72034) | 2018.3 |
| (Xilinx Answer 71718) | v1.3 (Rev. 71718) | 2018.2 |
| (Xilinx Answer 71191) | v1.3 (Rev. 71191) | 2018.1 |
| (Xilinx Answer 70012) | v1.3 (Rev. 70012) | 2017.3 |
| (Xilinx Answer 69405) | v1.2 (Rev.69405) | 2017.2 |
| (Xilinx Answer 69155) | v1.2 (Rev. 69155) | 2017.1 |
| (Xilinx Answer 68478) | v1.1 (Rev. 68478) | 2016.4 |
| (Xilinx Answer 68310) | v1.1 (Rev. 68310) | 2016.3 |
| (Xilinx Answer 68112) | v1.1 (Rev. 68112) | 2016.3 |
| (Xilinx Answer 68069) | v1.1 (Rev. 68069) | 2016.3 |
| (Xilinx Answer 67712) | v1.1(Rev 67712) | 2016.2 |
| (Xilinx Answer 67617) | v1.1 (Rev 67617) | 2016.2 |
| (Xilinx Answer 67307) | v1.1(Rev 67307) | 2016.1 |
| (Xilinx Answer 67144) | v1.1 (Rev 67144) | 2016.1 |
| (Xilinx Answer 65721) | v1.0 (Rev1) | 2015.3 |
Known and Resolved Issues
The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2015.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 72060) | MSI-X Internal Table access can cause Completion Time-out in Gen3 x16 Configuration | v1.3 (Rev1) | Not Resolved Yet Tactical Patch Provided |
| (Xilinx Answer 71877) | Reconfigurable Stage-2 support for Tandem PCIe w/ Field Updates | v1.3 (Rev4) | Not Resolved Yet |
| (Xilinx Answer 72034) | Allow Gen2 (5.0 GT/s) and 125 MHz AXI Clock Frequency with the xqzu5ev-ffrb900-1M-m device | v1.3 (Rev4) | Not Resolved Yet Tactical Patch Provided |
| (Xilinx Answer 71718) | x4 Gen3 Root Port IP generation fails in XAZU5EV-SFVC784-1Q-q device | v1.3 (Rev3) | v1.3 (Rev4) |
| (Xilinx Answer 71191) | Link does not train in Gen1 design with Refclk at 125MHz & 250MHz speeds | v1.3 (Rev2) | v1.3 (Rev3) |
| (Xilinx Answer 70012) | Tactical patch for issue fixes and enhancements | v1.3 | v1.3(Rev1) |
| (Xilinx Answer 69405) | Tactical patch for issue fixes and enhancements | v1.2(Rev1) | v1.3 |
| (Xilinx Answer 69155) | Gen3x16 support for -2L devices | v1.2 | v1.3(Rev1) |
| (Xilinx Answer 69063) | Gen3x16 configuration support on Virtex UltraScale+ -2LV (0.72v) Devices | v1.2 | v1.3(Rev1) |
| (Xilinx Answer 68478) | x16 Support in xczu7ev (fbv900 and ffvc1156) Devices | v1.1 (Rev2) | v1.2(Rev1) |
| (Xilinx Answer 68310) | Link training failure when "System Reset Polarity" is set to "active high" | v1.1(Rev2) | v1.2(Rev3) |
| (Xilinx Answer 68112) | MSI-X Vector Table and PBA | v1.1 (Rev2) | v1.1 (Rev3) |
| (Xilinx Answer 68069) | CPLL Calibration Block Integration and MSI-X Core GUI Issue | v1.1 (Rev2) | v1.2 |
| (Xilinx Answer 67712) | Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs: | v1.1 (Rev1) | v1.1(Rev2) |
| (Xilinx Answer 67617) | X16Gen3 Support for -1L and -2L devices | v1.1 (Rev1) | v1.3(Rev1) |
| (Xilinx Answer 67307) | Tactical patch with various fixes | v1.1 | v1.1 (Rev1) |
| (Xilinx Answer 67307) | Various Fixes | V1.1 | v1.1 (Rev1) |
| (Xilinx Answer 67144) | Incorrect GT Quad Location for Virtex 9P Devices | v1.1 | v1.1 (Rev1) |
Other Information:
| (Xilinx Answer 68134) | UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide |
| (Xilinx Answer 69453) | Hot Plug Support |
| (Xilinx Answer 71446) | Link Up Issue with Dell 5810 Systems |
| (Xilinx Answer 71732) | pcie_rq_tag_vld1 behavior in Internal Tag Management mode when straddle option is disabled |
| (Xilinx Answer 72043) | UltraScale+ PCI Express Integrated Block (Vivado 2018.3) - How to enable routing of messages on CQ interface? |
| (Xilinx Answer 71730) | Clock Sharing with sys_clk requirements |
| (Xilinx Answer 71994) | Zynq UltraScale+ RFSoC Tandem Prom Support |
| (Xilinx Answer 72175) | Debug Questions for Link Training Issues |
| (Xilinx Answer 72471) | Integrated Debugging Features and Usage Guide |
Revision History:
| 10/22/2015 | Initial Release |
| 04/13/2016 | Updated for 2016.1 Release |
| 05/14/2016 | Added (Xilinx Answer 67144) |
| 06/08/2016 | Updated for 2016.2 Release |
| 08/06/2016 | Added (Xilinx Answer 67617) |
| 08/16/2016 | Added (Xilinx Answer 67712) |
| 10/05/2016 | Updated for 2016.3 Release |
| 10/30/2016 | Added (Xilinx Answer 68112) |
| 02/03/2017 | Added (Xilinx Answer 68478) |
| 01/24/2017 | Updated for 2016.4 Release |
| 04/05/2017 | Updated for 2017.1 Release |
| 07/05/2017 | Updated for 2017.2 Release |
| 08/14/2017 | Added (Xilinx Answer 69405) |
| 11/15/2017 | Added (Xilinx Answer 70012) |
| 02/11/2018 | Updated Version Resolved section |
| 06/12/2018 | Added (Xilinx Answer 71191) |
| 08/21/2018 | Added (Xilinx Answer 71446) |
| 11/14/2018 | Added (Xilinx Answer 71718) |
| 02/20/2019 | Added (Xilinx Answer 72034) |
| 02/27/2019 | Added (Xilinx Answer 71730) |
| 02/28/2019 | Added (Xilinx Answer 71877) |
| 03/28/2019 | Added (Xilinx Answer 72060) |
| Answer Number | アンサータイトル | 問題の発生したバージョン | 修正バージョン |
|---|---|---|---|
| 70012 | DMA/Bridge Subsystem for PCI Express および UltraScale+ PCI Express Integrated Block (Vivado 2017.3) - 問題の修正および機能の改善を含めた緊急パッチ | N/A | N/A |
| AR# 65751 | |
|---|---|
| 日付 | 08/23/2019 |
| ステータス | アクティブ |
| 種類 | リリース ノート |
| IP | |