UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6584

LOGIBLOX, SIMPRIM, 4K - Timing simulation of the counter doesn't work; all outputs are "X."

説明

Keywords: LogiBLOX, counter, X

Urgency: Standard

General Description:
I cannot simulate the LogiBLOX counter after the post route; all the outputs are "X".
Although GSR is toggled at the beginning of a timing simulation, and all
inputs are defined at the beginning of the simulation, the outputs are
always "X" and never change.

Functional simulation is sucessful using the same testbench.

ソリューション

The problem is due to not asserting GSR for a sufficiently long time.
You must assert GSR for at least 100ns.

AR# 6584
作成日 08/31/2007
最終更新日 02/15/2001
ステータス アーカイブ
タイプ ??????