UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67103

UltraScale Boards and Kits - VADJ behaviour and bring-up

説明

How is the VADJ rail treated on UltraScale Boards and Kits?

ソリューション

For UltraScale Boards and Kits, the process for VADJ read as defined in VITA57.1 FMC specification is followed.

This involves the querying of the Mezzanine Card's EPROM to ensure that the VADJ voltage is brought up at the correct voltage.


The Maxim Integrated power controllers on the UltraScale Boards and Kits power on with VADJ off by design.

VADJ gets enabled by the MSP430 System Controller after power-on under the following conditions (1 or 2 or 3):


  1. If no FMC cards are plugged into the UltraScale board FMC connectors

  2. If one FMC card is plugged into either of the 2 FMC connectors on the UltraScale board
    AND
    Proper IPMI format defined in VITA57.1 FMC specification is programmed into the Mezzanine Card's EPROM
    AND
    The Mezzanine Card's IPMI data defines a compatible VADJ voltage (range) with the UltraScale board's VADJ capability

  3. If two FMC cards are plugged into the two UltraScale board FMC connectors
    AND
    Proper IPMI format defined in the VITA57.1 FMC specification is programmed into both of the Mezzanine Card's EPROMs
    AND
    Both Mezzanine Card's IPMI data defines a VADJ voltage (range) compatible with the UltraScale board's VADJ capability

アンサー レコード リファレンス

マスター アンサー レコード

AR# 67103
日付 05/20/2016
ステータス アクティブ
種類 一般
Boards & Kits 詳細 概略
このページをブックマークに追加