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AR# 6799

MAP: 1.5i/2.1i, FPGA Express: basnccomp.c:3346:1.1.2.4-cannot find other bel. . .

説明

Keywords: basnccomp, map, FPGA Express, Virtex, block RAM

Urgency: Standard

General Description:
When instantiating a BlockRAM component in an HDL design synthesized by
FPGA Express, the following error may occur in MAP:

FATAL_ERROR:Ncd:basnccomp.c:3346:1.1.2.4 - Cannot find other bel for
unconnected pin on bel BEL_dp256x32_1/BU0.BLOCKRAMB:31 of comp
dp256x32_1/BU0. Its current programmed state is : WEAMUX:0 ENAMUX:ENA
RSTAMUX:0 WEBMUX:WEB RSTBMUX:0 PORTB_ATTR:256X16 PORTA_ATTR:256X16 ENBMUX:1
Process will terminate.

ソリューション

1

This error may be due to unconnected clock pins on the RAM component, even if connections are
implied in the source HDL.

The workaround is to instantiate global clock buffers before the clock pins of the Block RAM instances.

2

A second possibility is to define the ports and their directions for the RAM component in a separate
module, like so:


module dp256x32( ADDRA, ADDRB, DIB, DIA, WEA, WEB, CLKA,
CLKB, RSTA, RSTB, ENA, ENB, DOA);

input [7:0] ADDRA, ADDRB;
input [31:0] DIB, DIA;
input WEA, WEB, CLKA, CLKB, RSTA, RSTB, ENA, ENB;
output [31:0] DOA;
endmodule

AR# 6799
作成日 06/17/1999
最終更新日 08/27/2001
ステータス アーカイブ
タイプ 一般