General Description: When instantiating a BlockRAM component in an HDL design synthesized by FPGA Express, the following error may occur in MAP:
FATAL_ERROR:Ncd:basnccomp.c:3346:188.8.131.52 - Cannot find other bel for unconnected pin on bel BEL_dp256x32_1/BU0.BLOCKRAMB:31 of comp dp256x32_1/BU0. Its current programmed state is : WEAMUX:0 ENAMUX:ENA RSTAMUX:0 WEBMUX:WEB RSTBMUX:0 PORTB_ATTR:256X16 PORTA_ATTR:256X16 ENBMUX:1 Process will terminate.
This error may be due to unconnected clock pins on the RAM component, even if connections are implied in the source HDL.
The workaround is to instantiate global clock buffers before the clock pins of the Block RAM instances.
A second possibility is to define the ports and their directions for the RAM component in a separate module, like so: