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AR# 6808

FPGA Express 3.2: Pullup/pulldown/keeper for Virtex are incorrectly written to the netlist

説明

Keywords: FPGA Express, pullup, pulldown, keeper, Virtex, netlist

Urgency: Standard

General Description:
When you instantiate a Pullup or Keeper for input port, FPGA Express version 3.1
connects it after IBUF instead of before IBUF. Consequently, M1 mapper
optimizes them away.

This problem has gone away in FPGA Express version 3.4.

ソリューション

1

Use EPIC/FPGA Editor to insert desired component in the IOB.

2

Use a temporary signal to connect the Pullup, then connect this signal to the
input. This solution does not work for the Keeper component.

Sample VHDL code:


Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity pullvhd is
port (A1, A2 : in std_logic;
B : out std_logic);
end test;

architecture RTL of pullvhd is

component PULLUP
port (O : out STD_LOGIC);
end component;

signal temp : std_logic;

begin

temp <= A1;
B <= A1 and A2;

U1: PULLUP port map (O => temp);

end RTL;



Sample Verilog code:


module pullv (A1, A2, B);
input A1, A2;
output B;
wire B;
wire temp;

PULLUP U1 (.o(temp));

assign temp = A1;
assign B = A1 & A2;

endmodule
AR# 6808
作成日 06/21/1999
最終更新日 08/27/2001
ステータス アーカイブ
タイプ 一般