We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6808

FPGA Express 3.2: Pullup/pulldown/keeper for Virtex are incorrectly written to the netlist


Keywords: FPGA Express, pullup, pulldown, keeper, Virtex, netlist

Urgency: Standard

General Description:
When you instantiate a Pullup or Keeper for input port, FPGA Express version 3.1
connects it after IBUF instead of before IBUF. Consequently, M1 mapper
optimizes them away.

This problem has gone away in FPGA Express version 3.4.



Use EPIC/FPGA Editor to insert desired component in the IOB.


Use a temporary signal to connect the Pullup, then connect this signal to the
input. This solution does not work for the Keeper component.

Sample VHDL code:

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pullvhd is
port (A1, A2 : in std_logic;
B : out std_logic);
end test;

architecture RTL of pullvhd is

component PULLUP
port (O : out STD_LOGIC);
end component;

signal temp : std_logic;


temp <= A1;
B <= A1 and A2;

U1: PULLUP port map (O => temp);

end RTL;

Sample Verilog code:

module pullv (A1, A2, B);
input A1, A2;
output B;
wire B;
wire temp;

PULLUP U1 (.o(temp));

assign temp = A1;
assign B = A1 & A2;

AR# 6808
日付 08/27/2001
ステータス アーカイブ
タイプ 一般