We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69037

UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the RLDRAM3 UltraScale and UltraScale+ cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the programmable logic RLDRAM3 IP core supported in UltraScale and UltraScale+ based devices.



Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

RLDRAM3 VersionVivado Tools Version
v1.4 (Rev. 8)
v1.4 (Rev. 7)2019.1
v1.4 (Rev. 6)2018.3
v1.4 (Rev. 5)2018.2
v1.4 (Rev. 4)2018.1
v1.4 (Rev. 3) 2017.4
v1.4 (Rev. 2)2017.3
v1.4 (Rev. 1)2017.2
v1.3 (Rev. 1)2016.4
v1.2 (Rev. 1)2016.2
v5.0 (Rev. 1)2014.2

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page.

For a complete list of supported RLDRAM3 memory devices refer to the memory_device_support_rldram3.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

Table 2 provides a list of post-2015.1 MIG UltraScale RLDRAM3 IP patches that are recommended be installed if currently in production but are unable to upgrade the IP to 2016.1.

All other users are recommended to upgrade to 2016.1.

Table 3 provides the known and resolved issues for the UltraScale family RLDRAM3 IP.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: RLDRAM3 IP Patches

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69438)UltraScale/UltraScale+ RLDRAM3 IP v1.4 - Vivado 2016.4 and 2017.x - Previously working interface now fails calibration at Write DQ/DM Deskew stepv1.4
(Xilinx Answer 70214)UltraScale/UltraScale+ - RLDRAM3 IP - Tactical Patch for SEM and RLD integrationv1.3N/A 
(Xilinx Answer 66689)UltraScale RLDRAM3 IP - patch update recommended for 2015.4v1.1v2.0
(Xilinx Answer 66688)UltraScale RLDRAM3 IP - patch update recommended for 2015.3v1.0v2.0
(Xilinx Answer 66035)MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.2v7.1v2.0
(Xilinx Answer 66034)MIG UltraScale RLDRAM3 IP - patch update recommended for 2015.1v7.0v2.0

Table 3: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 72230)UltraScale/UltraScale+ - RLDRAM3 IP - Known Issues with RLDRAM3 and SEM IP Interactionv1.3No Plan To Fix
(Xilinx Answer 67922)UltraScale RLDRAM3 - Advanced Traffic Generator (ATG) detects data compare errors when testing with the TG_MAX_NUM_OF_ITER_ADDR parameter is set to a large value
v1.2 (Rev. 1)NAB
(Xilinx Answer 67367)UltraScale RLDRAM3 - when targeting 576Mb and 1.125Gb x36 parts an extra address bit exists on the pin outv1.2v1.3
(Xilinx Answer 67125)UltraScale RLDRAM3 - spec violation allowed for Read Latency (RL) of 15 and -107 speed binv1.2v1.2 (Rev. 1)
(Xilinx Answer 66589)UltraScale RLDRAM3 - ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. v1.1v1.2
(Xilinx Answer 65371)UltraScale RLDRAM3 - hardware failures can occur at lower frequencies of operationv1.0v1.2
(Xilinx Answer 65787)UltraScale RLDRAM3 - Calibration failures can occur when Data Mask (DM) is disabledv1.0v1.1
(Xilinx Answer 65651)UltraScale RLDRAM3 - Read Latency of 17 is not a valid value for "-093E' parts
(Xilinx Answer 65219)UltraScale RLDRAM3 - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3v1.0No Plan To Fix
(Xilinx Answer 64946)UltraScale RLDRAM3 - PCB pull-down required on RESET#
(Xilinx Answer 64772)UltraScale RLDRAM3 - timing failures in mmcm_clk0 domain as a result of too many logic levelsv7.1v1.0
(Xilinx Answer 64486)UltraScale RLDRAM3 - tWTR violations seen at frequencies greater than 750MHzv7.0v1.0
(Xilinx Answer 64642)UltraScale RLDRAM3 - IP upgrade in 2015.1 creates DDR4 controllerv7.0v7.1
(Xilinx Answer 62593)UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanesv6.0v7.0
(Xilinx Answer 63596)UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1
(Xilinx Answer 63687)UltraScale RLDRAM3 - IDELAY taps do not move during QVLD Calibration which can cause data errors in hardwarev6.1v7.0
(Xilinx Answer 63238)UltraScale RLDRAM3 - Tactical Patch - timing failures in mmcm_clkout0 domainv6.1v7.0
(Xilinx Answer 61627)UltraScale RLDRAM3 - data mask does not work for RLDRAM3 designs
v5.0 (Rev .1)v6.0
(Xilinx Answer 60951)UltraScale RLDRAM3/QDRII+ - Timing failure from XiPHY to riu_clk
v5.0 (Rev. 1)v6.0

Revision History:

04/18/2017Created Separate Answer Record for RLDRAM3
06/12/2017Updated for 2017.2; Added AR68028, AR69291
06/22/2017Added AR69324
07/31/2017Updated debugging link to AR#68937
09/18/2017Updated formatting and updated for 2017.3
11/29/2017Updated for 2017.4
03/13/2018Updated for 2018.1
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1; Added AR#72230
10/21/2019Updated for 2019.2



タイトル サイズ ファイルタイプ
memory_device_support_rldram3.xlsx 17 KB XLSX

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
60951 UltraScale RLDRAM3 および QDRII+ - XiPHY から riu_clk でタイミング エラーが発生する N/A N/A
61627 UltraScale RLDRAM3 - RLDRAM3 デザインでデータ マスクが使用できない N/A N/A
63238 UltraScale RLDRAM3 - 緊急パッチ - mmcm_clkout0 ドメインのタイミング エラー N/A N/A
63687 MIG UltraScale RLDRAM3 - QVLD キャリブレーション中に IDELAY タップが移動せず、ハードウェアでデータ エラーが発生することがある N/A N/A
63596 UltraScale DDR4/DDR3/RLDRAM3 - 2014.4.1 を使用しているとホールド違反が発生する可能性がある N/A N/A
62593 UltraScale RLDRAM3 - 72 ビット デザインのデフォルトのバンク選択ではすべてのデータ バイト レーンが選択されない N/A N/A
64642 UltraScale RLDRAM3 - IP を 2015.1 にアップグレードすると DDR4 コントローラーが作成される N/A N/A
64486 UltraScale RLDRAM3 - 周波数が 750 MHz より高い場合に tWTR 違反が発生する N/A N/A
67125 UltraScale RLDRAM3 - 15 の読み出しレイテンシ (RL) および -107 のスピード ビンに対して仕様違反が許可される N/A N/A
64946 UltraScale RLDRAM3 - RESET# に PCB プルダウン抵抗が必要である N/A N/A
65219 UltraScale RLDRAM3 - 古いバージョンの MIG UltraScale RLDRAM IP を使用すると 2015.3 でクリティカル警告メッセージが表示される N/A N/A
65651 UltraScale RLDRAM3 - 読み出しレイテンシ 17 は -093E パーツに有効な値ではない N/A N/A
65787 UltraScale RLDRAM3 - データ マスク (DM) を無効にすると、キャリブレーション エラーが発生する N/A N/A
66589 UltraScale RLDRAM3 - 「[Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.」というエラー メッセージが表示される N/A N/A
67922 UltraScale RLDRAM3 - TG_MAX_NUM_OF_ITER_ADDR パラメーターに大きな値を設定してテストを実行すると Advanced Traffic Generator (ATG) でデータ比較エラーが検出される N/A N/A
66034 MIG UltraScale RLDRAM3 - 2015.1 の推奨パッチ アップデート N/A N/A
66035 MIG UltraScale RLDRAM3 - Vivado 2015.2 の推奨パッチ アップデート N/A N/A
66688 UltraScale RLDRAM3 IP - Vivado 2015.3 の推奨パッチ アップデート N/A N/A
64772 UltraScale RLDRAM3 - 数多くのロジック レベルが存在するために mmcm_clk0 ドメインでタイミング エラーが発生する N/A N/A
65371 UltraScale RLDRAM3 - 動作周波数が低いとハードウェア エラーが発生する可能性がある N/A N/A
66689 UltraScale RLDRAM3 IP - Vivado 2015.4 の推奨パッチ アップデート N/A N/A
71697 UltraScale+ RFSoC DDR4/DDR3/RLDRAM3 - FSVE1156 パッケージで間違ったデータ幅が使用できてしまう N/A N/A
72230 UltraScale/UltraScale+ - RLDRAM3 IP - RLDRAM3 と SEM IP が共存する場合の既知の問題 N/A N/A
AR# 69037
日付 10/24/2019
ステータス アクティブ
種類 リリース ノート
デバイス 詳細 概略