UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7006

Foundation1.5is2,FPGAExpress3.1: How to get report of synthesis result in Foundation HDL macros

説明

Keywords: synthesis result for macros, HDL macros

Urgency: Standard

General Description:
In Foundation standard with Express package (FND-EXP),
the tool will report synthesis result such as Primitive reference
count in HDL flow (top level HDL) only. How do you get report
of synthesis result of your HDL macro in a schematic design ?

ソリューション

1) In HDL editor click on
Synthesis -> Options, and check on the box next to "Show Constraint Editor"

2) After synthesizing your module as a macro, you can find the report of the synthesis result as :
<Project>\DPMCOMP.TMP\chips\<modulenae>_OPT\<modulename>OPT.trt

E.G., If your project name is "test" and the module name
is "bla" the report file will be

test\DPMCOMP.TMP\chips\bla_OPT\bla_OPT.trt file.

NOTE: The trt file is generated only when you specify to show the
constraint editor. Thus FND-BSX package do not have this feature.
AR# 7006
作成日 07/12/1999
最終更新日 06/13/2002
ステータス アーカイブ
タイプ 一般