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AR# 7017

WebPACK - Can I use a VHDL or Verilog source file, or is the tool ABEL-based?

説明

Can I use a VHDL or Verilog source file, or is the tool ABEL-based?

ソリューション

WebPACK 10 and earlier supports synthesis in three HDL formats: ABEL, VHDL, and Verilog.  

 

WebPACK 11 and Later supports Verilog and VHDL synthesis.

AR# 7017
作成日 08/21/2007
最終更新日 05/14/2014
ステータス アーカイブ
タイプ 一般