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AR# 70927

Queue DMA subsystem for PCI Express (PCIe) - Release Notes and Known Issues for Vivado 2018.1 and newer tool versions

説明

This answer record contains the Release Notes and Known Issues for the DMA Subsystem for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tool versions.

 

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

ソリューション

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • PCIe DMA Subsystem Product Guide (PG302)

 

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v3.0 (Rev1) 2019.1
v3.0 2018.3
v2.0 2018.2
v1.0
2018.1

 

Tactical Patch

The following table provides a list of tactical patches for the DMA Subsystem for PCI Express core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version
(Xilinx Answer 71375)
v2.0 (Rev. 71375)
2018.2
(Xilinx Answer 71421) v2.0 (Rev. 71421) 2018.2
(Xilinx Answer 71601) v2.0 (Rev. 71601)
2018.2
(Xilinx Answer 71637)
v2.0 (Rev. 71637) 2018.2
(Xilinx Answer 72013) v2.0 (Rev. 72013) 2018.3
(Xilinx Answer 72436) v3.0 (Rev 72436) 2019.1

 

Note:

  • For a given Vivado version, the latest patch consists of fixes in all previous patches for that Vivado version and all also fixes in patches for previous Vivado versions. The table below gives a detailed description of the patches.

Design Advisory

(Xilinx Answer 70838) Design Advisory for AXI SmartConnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption

 

Known and Resolved Issues

The following table provides known issues for the DMA Subsystem for PCI Express core, starting with v1.0, initially released in Vivado 2018.1.

Note: The "Version Found" column lists the version the problem was first discovered.

 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 72436) Tactical Patch for Issue Fixes:

  • XSIM Simulation issue.
  •  Enable Gen4 option in the GUI for HBM PCIe blocks
v3.0 (Rev1) Not Resolved Yet; Tactical Patch Provided
(Xilinx Answer 72412) Timing failure on certain devices with specific configurations v3.0 (Rev1) Not Resolved Yet
(Xilinx Answer 72013) Tactical Patch for Issue Fixes:

  • Mailbox interrupt issue fix: Mailbox interrupts were generating only from PF vectors and were not able to generate from other vectors
  • Interrupts not received properly with mix of direct interrupts and indirect interrupts
  • AXI-MM only with completion option not working
  • Write back coalesce buffer depth of 32 and 64 not working, 32 depth issue is fixed and 64 depth is not allowed
  • Prefetch cache depth GUI parameter propagation issue
  • C2H write back timer deletion issue: Injection of a timer immediately after deletion causes deletion to stall and resulting in multiple timers
  • Marker response not working when queue is disabled
  • Issue with more than 8 interrupt vectors per function using Tcl option CONFIG.adv_int_usr
  • Expansion ROM space (EPROM selected in last BAR) read/write access issue
  • Example design issue: Completions are not received for ST C2H transfers which follows mix payload transfers (immediate data and payload data)
  • Removed empty cycle after SOP in C2H DMA write engine to improve performance

v3.0
v3.1 (Rev1)
 
(Xilinx Answer 71637) Tactical Patch for Issue Fixes:

  • Bug Fix: AXI MM descriptor bypass in port(is_wb) tieoff
v2.0
v3.0
(Xilinx Answer 71601) Tactical Patch for Issue Fixes:

  • Bug Fix: Performance example design update
  •  Feature Enhancement: Descriptor bypass example design addition
v2.0
v3.0
(Xilinx Answer 71421) Tactical Patch for Issue Fixes:

  • Descriptor Engine and Prefetch Engine deadlock
  • Completion Timers Issue
  • Eviction of Prefetch Descriptors Issue
  • Credit Coalescing Issue
  • C2H QID0 Issue
  • Outstanding data based request throttling in Streaming H2C Engine
  • User+Timer+Count trigger mode in C2H Completion Engine
v2.0
v3.0
(Xilinx Answer 71375) Tactical Patch for Issue Fixes:

Bug Fix: Fixed issue with propagating ext_sys_clk_bufg down to the base PCIe core level in UltraScale+ PCI Express 4c Integrated Block devices.
v2.0
v3.0
(Xilinx Answer 70951)
Gen3x16 configuration incorrectly enabled in the core generation GUI for -1,-1L,-1LV,-2LV devices
v1.0
v2.0
(Xilinx Answer 71181) XSIM Simulation Support v1.0
v3.0

 

Other Information:

(Xilinx Answer 70928)
Queue DMA subsystem for PCI Express (PCIe) Drivers
(Xilinx Answer 71453) Queue DMA Performance Report
(Xilinx Answer 71554) [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I1
(Xilinx Answer 71737) QDMA Vivado 2018.2 to 2018.3 Migration Guide
(Xilinx Answer 72352) Tcl options for additional IP features
(Xilinx Answer 72813) Read file: Input/output error

 

Revision History:

04/18/2018 Initial Release
06/09/2018 Added (Xilinx Answer 71181)
08/08/2018 Added (Xilinx Answer 71375)
08/25/2018 Added (Xilinx Answer 71421)
10/05/2018 Added (Xilinx Answer 71601)
10/30/2018 Added (Xilinx Answer 71637)
11/14/2018 Added (Xilinx Answer 71554)
12/14/2018 Added (Xilinx Answer 71737)
03/11/2019 Added (Xilinx Answer 72013)
06/18/2019 Added (Xilinx Answer 72436)
AR# 70927
日付 10/02/2019
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